Patents by Inventor Kuo-Chang Yang

Kuo-Chang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10916866
    Abstract: A coaxial cable connector includes a hexagonal body on an outer portion of nut of a coupling head; an opening spring washer combined with a sleeve of the coupling head; an inner tube shaft threaded through the coupling head and assembled with a joint seat; the inner tube shaft set with a center through-hole and including a tapered bevel disposed in a front portion and a clamping layer which is disposed in an inner hole of a tail portion, and a colored flat tire ring. The joint seat is threaded through the inner tube shaft to an end surface layer of the tail portion, and an isolation net of the coaxial cable is turn back onto an outer cover to the tapered bevel. A contraction ring is combined with a chamfer and a bevel of the sleeve to form a gapless tightness.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 9, 2021
    Assignee: BNS Precision Industry Co., LTD.
    Inventor: Kuo Chang Yang
  • Patent number: 9865727
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 9, 2018
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 9768274
    Abstract: A method includes defining, on a surface of a material, a plurality of discrete portions of a surface as surface elements having at least one of a laterally-varying size, a laterally-varying shape, and a laterally-varying spacing. A plurality of portions of the material beneath the surface elements are doped with a single quantity of dopant material per element area. The dopant material within the material beneath the surface elements expands to provide a lateral gradient of dopant material in the material beneath the surface elements.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: September 19, 2017
    Assignee: Power Integrations, Inc.
    Inventors: Wayne B. Grabowski, Kuo-Chang Yang, Kamal Raj Varadarajan, Sujit Banerjee, Vijay Parthasarathy
  • Publication number: 20170062606
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Applicant: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 9496386
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 15, 2016
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Publication number: 20160149018
    Abstract: A method includes defining, on a surface of a material, a plurality of discrete portions of a surface as surface elements having at least one of a laterally-varying size, a laterally-varying shape, and a laterally-varying spacing. A plurality of portions of the material beneath the surface elements are doped with a single quantity of dopant material per element area. The dopant material within the material beneath the surface elements expands to provide a lateral gradient of dopant material in the material beneath the surface elements.
    Type: Application
    Filed: April 13, 2015
    Publication date: May 26, 2016
    Inventors: Wayne B. Grabowski, Kuo-Chang Yang, Kamal Raj Varadarajan, Sujit Banerjee, Vijay Parthasarathy
  • Publication number: 20150340454
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Application
    Filed: August 3, 2015
    Publication date: November 26, 2015
    Applicant: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 9117899
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 25, 2015
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Publication number: 20140145245
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 8704296
    Abstract: In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Robert Kuo-Chang Yang
  • Patent number: 8592906
    Abstract: A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: November 26, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mohamed N. Darwish, Robert Kuo-Chang Yang
  • Patent number: 8580644
    Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Publication number: 20130221429
    Abstract: In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Inventor: Robert Kuo-Chang Yang
  • Patent number: 8299395
    Abstract: A laser marking machine includes a support portion, a laser marking device fixed on the support portion, a control chip and a fixing mechanism fixed on the support portion. The fixing mechanism includes a support board configured for supporting a workpiece, and four positioning blocks moved, and four motors being able to control the four positioning blocks to slide in the support board. The fixing mechanism further includes at least two position detectors. The two position detectors are able to position detector a distance data of the workpiece deviating from a center of the support board along X and Y axes, and transmit the distance data to the control chip. The control chip analyzes the distance data to control the four motors to respectively drive the four positioning blocks to slide in the support board until the workpiece is centered on the support board.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: October 30, 2012
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Kuo-Chang Yang, Song-Ya Chen, Dong-Wei Zhao, Qun-Fang Chen
  • Publication number: 20120211834
    Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
    Type: Application
    Filed: May 1, 2012
    Publication date: August 23, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Patent number: 8226179
    Abstract: A housing comprises a first outer shell, a second outer shell; and a hook configuration configured for assembling the first outer shell on the second outer shell. The hook configuration comprises two clasp units set in the first outer shell. Each of the two clasp units comprises a first clasp body and a first magnet. Two hook units are set in the second outer shell. Each of the two hook units comprises a first hook and a second magnet.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: July 24, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Kuo-Chang Yang, Yi-Wen Wei
  • Publication number: 20120146140
    Abstract: A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 14, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Mohamed N. Darwish, Robert Kuo-Chang Yang
  • Patent number: 8193565
    Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Publication number: 20120091516
    Abstract: Voltage termination structures include one or more capacitively coupled trenches, which can be similar to the trenches in the drift regions of the active transistor. The capacitively coupled trenches in the termination regions are arranged with an orientation that is either parallel or perpendicular to the trenches in the active device drift region. The Voltage termination structures can also include capacitively segmented trench structures having dielectric lined regions filled with conducting material and completely surrounded by a silicon mesa region. The Voltage termination structures can further include continuous regions composed entirely of an electrically insulating layer extending a finite distance vertically from the device surface.
    Type: Application
    Filed: April 11, 2011
    Publication date: April 19, 2012
    Inventors: Robert Kuo-Chang Yang, Sunglyong Kim, Joseph A. Yedinak
  • Publication number: 20120080410
    Abstract: A laser marking machine includes a support portion, a laser marking device fixed on the support portion, a control chip and a fixing mechanism fixed on the support portion. The fixing mechanism includes a support board configured for supporting a workpiece, and four positioning blocks moved, and four motors being able to control the four positioning blocks to slide in the support board. The fixing mechanism further includes at least two position detectors. The two position detectors are able to position detector a distance data of the workpiece deviating from a center of the support board along X and Y axes, and transmit the distance data to the control chip. The control chip analyzes the distance data to control the four motors to respectively drive the four positioning blocks to slide in the support board until the workpiece is centered on the support board.
    Type: Application
    Filed: October 27, 2010
    Publication date: April 5, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., FU TAI HUA INDUSTRY (SHENZHEN) CO., LTD.
    Inventors: KUO-CHANG YANG, SONG-YA CHEN, DONG-WEI ZHAO, QUN-FANG CHEN