Abstract: The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having a first region and a second region; a first fin feature formed on the substrate within the first region; and a second fin feature formed on the substrate within the second region. The first fin feature includes a first semiconductor feature of a first semiconductor material formed on a dielectric feature that is an oxide of a second semiconductor material. The second fin feature includes a second semiconductor feature of the first semiconductor material formed on a third semiconductor feature of the second semiconductor material.

Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.

Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.

Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes an isolation feature over the substrate and over sides of the fin feature; a semiconductor oxide feature including the first semiconductor material and disposed on sidewalls of the first portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extending into recesses that are into a top portion of the semiconductor oxide feature and below the second portion of the fin feature.

Abstract: A semiconductor structure includes a substrate, at least one active fin present on the substrate, and at least one isolation dielectric surrounding the active fin. The isolation dielectric has at least one trench therein. The semiconductor structure further includes at least one dielectric liner present on at least one sidewall of the trench of the isolation dielectric, and at least one filling dielectric present in the trench of the isolation dielectric.

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

Abstract: A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.

Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

Abstract: A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

Abstract: A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.

Abstract: A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.

Abstract: Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a first gate structure formed across the fin structure. The semiconductor structure further includes a first source/drain structure formed in the fin structure adjacent to the first gate structure and a first contact formed over the first source/drain structure. In addition, the first contact includes a first extending portion extending into the first source/drain structure.

Abstract: A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on sidewalls of a portion of the fin. The method further includes forming a spacer layer over the sacrificial layer and recessing the portion of the fin past a bottom surface of the sacrificial layer. The recessing forms a trench disposed between sidewall portions of the spacer layer. At least a portion of the sacrificial layer is removed, and a source/drain region is formed in the trench.

Abstract: Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.