Patents by Inventor Kuo-Cheng Lee

Kuo-Cheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310686
    Abstract: Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.
    Type: Application
    Filed: September 23, 2021
    Publication date: September 29, 2022
    Inventors: Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220310528
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO
  • Publication number: 20220310550
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.
    Type: Application
    Filed: October 6, 2021
    Publication date: September 29, 2022
    Inventors: Chun-Liang LU, Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220310533
    Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.
    Type: Application
    Filed: September 17, 2021
    Publication date: September 29, 2022
    Inventors: Chun-Liang LU, Chun-Wei CHIA, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220302186
    Abstract: The present disclosure describes an image sensor device and a method for forming the same. The image sensor device can include a semiconductor layer. The semiconductor layer can include a first surface and a second surface. The image sensor device can further include an interconnect structure formed over the first surface of the semiconductor layer, first and second radiation sensing regions formed in the second surface of the semiconductor layer, a metal stack formed over the second radiation sensing region, and a passivation layer formed through the metal stack and over a top surface of the first radiation sensing region. The metal stack can be between the passivation layer and an other top surface of the second radiation sensing region.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Chien HSIEH, Hsin-Chi CHEN, Kuo-Cheng LEE, Yun-Wei CHENG
  • Publication number: 20220302187
    Abstract: Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Chiu-Jung Chen, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Volume Chien, Yun-Wei Cheng
  • Publication number: 20220293651
    Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Wei-Lin CHEN, Ching-Chung SU, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220293650
    Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20220293652
    Abstract: A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Wei-Lin CHEN, Ching-Chung SU, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220293557
    Abstract: Alignment of devices formed on substrates that are to be bonded may be achieved through the use of scribe lines between the devices, where the scribe lines progressively increase or decrease in size from a center to an edge of one or more of the substrates to compensate for differences in the thermal expansion rates of the substrates. The devices on the substrates are brought into alignment as the substrates are heated during a bonding operation due to the progressively increased or decreased sizes of the scribe lines. The scribe lines may be arranged in a single direction in a substrate to compensate for thermal expansion along a single axis of the substrate or may be arranged in a plurality of directions to compensate for actinomorphic thermal expansion.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Inventors: Hsi-Cheng HSU, Jui-Chun WENG, Ching-Hsiang HU, Ji-Hong CHIANG, Kuo-Hao LEE, Chia-Yu LIN, Chia-Chun HUNG, Yen-Chieh TU, Chien-Tai SU, Hsin-Yu CHEN
  • Patent number: 11444116
    Abstract: A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Publication number: 20220278143
    Abstract: A pixel sensor may include a main deep trench isolation (DTI) structure and one or more sub-DTI structures in a substrate of the pixel sensor to increase the quantum efficiency of the pixel sensor at large incident angles. The one or more sub-DTI structures may be located within the perimeter of the main DTI structure and above a photodiode. The one or more sub-DTI structures may be configured to provide a path of travel for incident light into the photodiode from large incident angles in that the one or more sub-DTI structures may be filled with an oxide material to increase light penetration into the one or more sub-DTI structures. This may reduce reflections at a top surface of the substrate, thereby permitting incident light to refract into the substrate and toward the photodiode.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220271076
    Abstract: A photosensor includes a substrate, a photo-detecting column, a gate structure, a floating node structure and a channel structure. The substrate has a first doping type. The photo-detecting column has a second doping type and is disposed in the substrate. The gate structure is disposed on the substrate in a vertical direction, and is electrically insulated from the photo-detecting column. The floating node structure is disposed on the gate structure opposite to the photo-detecting column in the vertical direction, and is electrically insulated from the gate structure. The channel structure extends through the gate structure, is electrically insulated from the gate structure, and is electrically connected to the photo-detecting column and the floating node structure.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: P.C. CHANG, Ping-Hao LIN, Kuo-Cheng LEE
  • Patent number: 11415878
    Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Chiu-Hua Chung, Sheng-Yuan Lin, Hsin-Yu Chen
  • Publication number: 20220238715
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Patent number: 11392024
    Abstract: A portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hao Lee, Hsi-Cheng Hsu, Jui-Chun Weng, Han-Zong Pan, Hsin-Yu Chen, You-Cheng Jhang
  • Patent number: 11389995
    Abstract: An injection molding method for a semifinished product includes a semifinished product emplacement step, a semifinished product pre-compression step and a forming step. First, a pair of mold with a forming space is provided. A semifinished product is put into the mold, and a first joint is performed to the mold by a press-fit jig, fixing the semifinished product in the forming space. The semifinished product is also tightly fitted with the mold. Next, a first open-die is performed and the press-fit jig is removed. After that, a second joint is performed, and a forming material is injected into the forming space. Finally, a second open-die is performed, and then a finished product is formed. By the semifinished product pre-compression step, the forming material can be prevented from resulting in spill or burr on the semifinished product, thereby improving the yield of injection molding.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: July 19, 2022
    Assignee: DRAGONSTATE TECHNOLOGY CO., LTD.
    Inventors: Kuo-Chi Lee, Chin-Hsing Lee, Lei Cheng
  • Patent number: 11380721
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 11367745
    Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 11355545
    Abstract: Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiu-Jung Chen, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Volume Chien, Yung-Lung Hsu, Yun-Wei Cheng