Patents by Inventor Kuo-Cheng Ting

Kuo-Cheng Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9093179
    Abstract: A method for improving test coverage of pads of a chip, where the chip includes a control unit, a plurality of pads, and a storage unit, and the storage unit includes a plurality of blocks, includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 28, 2015
    Assignee: Etron Technology, Inc.
    Inventors: Shih-Hsing Wang, Ming-Cheng Liang, Kuo-Cheng Ting
  • Publication number: 20140075251
    Abstract: A method capable of improving test coverage of chip pads, where the chip includes a control unit, a plurality of pads, and a storage unit, is disclosed. The storage unit includes a plurality of blocks. The method includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed.
    Type: Application
    Filed: April 18, 2013
    Publication date: March 13, 2014
    Applicant: Etron Technology, Inc.
    Inventors: Shih-Hsing Wang, Ming-Cheng Liang, Kuo-Cheng Ting
  • Patent number: 7817485
    Abstract: A testing system with data compressing function includes a third data end, a first encoder, and a second encoder. The testing system receives testing data and testing address for testing if any memory cell fails in a memory. The memory includes a first data end, a second end, and an address end. The first encoder encodes the testing data to the data type of the first data end according to the testing address. The second encoder encodes the testing data to the data type of the second data end according to the testing address. In this way, the corresponding memory cells of the first data and second ends store same testing data.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: October 19, 2010
    Assignee: Etron Technology, Inc.
    Inventors: Jen-Shou Hsu, Kuo-Cheng Ting
  • Publication number: 20090273996
    Abstract: A testing system with data compressing function includes a third data end, a first encoder, and a second encoder. The testing system receives testing data and testing address for testing if any memory cell fails in a memory. The memory includes a first data end, a second end, and an address end. The first encoder encodes the testing data to the data type of the first data end according to the testing address. The second encoder encodes the testing data to the data type of the second data end according to the testing address. In this way, the corresponding memory cells of the first data and second ends store same testing data.
    Type: Application
    Filed: November 13, 2008
    Publication date: November 5, 2009
    Inventors: Jen-Shou Hsu, Kuo-Cheng Ting