Abstract: The embodiments of the present disclosure relate to an electrode structure and OLED display. The electrode structure includes a first electrode layer, a second electrode layer and a third electrode layer. The first electrode layer includes at least one layer from Ti layer, Ti alloy layer, Zr layer and Zr alloy layer. The second electrode layer is formed on the first electrode layer. The third electrode layer is formed on the second electrode layer and includes at least one layer from Ti layer, Ti alloy layer, Zr layer and Zr alloy layer. The present disclosure saves massive rare metal indium, which can help to reduce the manufacture cost of OLED display. Meanwhile, it is not prone to delamination, rupture, exfoliation and so on at the first and third electrode layers, and thusly reduced light scattering due to Ti, Ti alloy, Zr or Zr alloy with good corrosion resistance.

Abstract: A clock generating circuit and method therefor are provided, which includes a control unit, a first oscillating module, a second oscillating module, a status control unit, and a multiplexer. The control unit is used for outputting a first control signal and a second control signal so as to drive the first oscillating module and the second oscillating module to generate or stop from a first clock signal and a second signal to the multiplexer.

Abstract: The present invention provides a method for accessing a memory device and a memory accessing device. The method includes a) providing the memory device having a plurality of memory sub-spaces respectively having a plurality of address ranges; b) respectively assigning a plurality of base addresses to the plurality of memory sub-spaces; c) inputting an access address; d) respectively operating the base addresses with the access address to obtain a plurality of operated results; and e) accessing one of the memory sub-spaces if a specific one of the operated results falls within one of the address ranges corresponding to the one memory sub-space.

Abstract: The mechanism includes a virtual address detecting circuit for detecting the virtual address of the instruction code. When a virtual address is detected, an indicating signal is generated, which is then sent to an indirect address register to register the indirect address of the instruction code. Thereafter, an indirect address replacing circuit is used to decode and replace the indirect address registered in and sent from the indirect address register with a direct address. In the absence of the virtual address, the direct address is allowed to pass through the indirect address replacing circuit.

Abstract: A voltage detector circuit for instantaneously detecting abnormal voltages in a micro controller includes a voltage detection circuit connected between the power supply and reset voltage ends of an internal circuit of the micro controller so as to instantaneously detect changes in the power supply, without the time delay associated with the external low pass filter that supplies the reset voltage. The detecting circuit is a logic "NOT" gate which has a power supply connecting end connected to a reset voltage end of the internal circuit, an input end connected to the power supply end of the internal circuit, and an output end connected to a cooperating input end of the latch circuit, so that the latch circuit latches a signal output by the voltage detector whenever an abnormal power supply voltage is detected, and outputs a flag signal to the micro controller to effect an instantaneous reset of the micro controller.

Abstract: An improved micro-controller with a built-in test circuit is disclosed.

Abstract: The present invention is related to a system reset device setting the reset status of a system in response to a reset signal. The system reset device according to the present invention includes a power-stability detecting circuit for detecting the stability of a power signal generated by a power source and provided for the system, an oscillation-stability detecting circuit for detecting the stability of an oscillation signal generated by an oscillator and provided for the system, and a level-control circuit electrically connected to the power-stability detecting circuit and the oscillation-stability detecting circuit for controlling a level state of the rest signal in response to the stability of the power signal and the oscillation signal. The level-control circuit includes an OR gate, an AND gate, and an S-R latch for performing the level state control of the reset signal.

Abstract: A timer which provides both the surveying and counting functions. It contains a counter, a multiplexer, an edge-triggered controller, a time-base latching circuit, and a pulse-detecting circuit. It not only can be used as a timer, but can also be used as a counter to count the number of the external signals so as to detect the width of an external signal.

Abstract: A memory table look-up method for executing a table look-up instruction in an active program uses an instruction buffer executing device, a controller and a data register to output table look-up data from a memory to the data register. The method includes causing an instruction buffer executing device to execute a table look-up instruction obtained from the memory and pre-stored in the instruction buffer executing device in a first cycle to generate and output a table look-up signal, and to cause the controller to output a next instruction being an instruction next to the table look-up instruction in the active program from the memory to the instruction buffer executing device in response to the table look-up signal.

Abstract: The present invention relates to a reset signal generator adapted to be used with a microprocessor for generating a reset signal to initialize the microprocessor, which includes an oscillator to generate a fixed clock signal, a counter electrically connected to the oscillator for generating a cyclic signal in response to the fixed clock signal and outputting the reset signal at an end of a period of the cyclic signal, and a clear signal generating device electrically connected to the counter and outputting a clear signal for the counter in response to an output signal from the microprocessor. The present invention ensures that when the microprocessor is abnormal or down it will be initialized by the reset signal.

Abstract: A flag setting circuit for a microcontroller, which can be set with a HALT mode flag and a watchdog timer overflow flag by using a system power-on signal, an external reset signal, a watchdog timer overflow signal inside the microcontroller, a clear instruction for watchdog timer, a HALT mode instruction, and a wake-up signal. The setting circuit for the watchdog timer overflow flag includes a reset signal generator, a watchdog timer, a clear signal generator, a flag clear circuit, and a register circuit. The setting circuit for the HALT mode flag includes a HALT mode discerning circuit, a flag clear circuit, and a register circuit. The frequency source of the watchdog timer is provided by means of a frequency from the system oscillator divided with four, or by using a frequency of RC oscillator built in the system. Under the HALT mode, the RC oscillator is selected. By means of the HALT mode flag and the watchdog timer overflow flag, the operation condition of the system hardware can be discerned.