Patents by Inventor Kuo-Chi Lin
Kuo-Chi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11939268Abstract: A method of forming low-k material is provided. The method includes providing a plurality of core-shell particles. The core of the core-shell particles has a first ceramic with a low melting point. The shell of the core-shell particles has a second ceramic with a low melting point and a low dielectric constant. The core-shell particles are sintered and molded to form a low-k material. The shell of the core-shell particles is connected to form a network structure of a microcrystal phase.Type: GrantFiled: December 23, 2020Date of Patent: March 26, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuo-Chuang Chiu, Tzu-Yu Liu, Tien-Heng Huang, Tzu-Chi Chou, Cheng-Ting Lin
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Publication number: 20240088195Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
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Publication number: 20240072158Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao, Kuo-Min Lin, Z.X. Fan, Chun-Jung Huang, Wen-Yu Kuo
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Publication number: 20230249263Abstract: A machine tool includes a cutting unit and multiple quick-release elements. The cutting unit includes a handle including two lateral facets, an upper facet, multiple bores made in the upper facet, and multiple cutouts made in at least one of the lateral facets. Each of the cutouts is in communication with a corresponding one of the bores. Each of the quick-release elements includes a cam including an operative portion located further from a rotational axis than an idle portion. Each of the cams is inserted in a corresponding one of the bores. The idle portion of each of the cams is located in the corresponding bore when each of the cams is at a first angle. The operative portion of each of the cams extends from the corresponding bore through the corresponding cutout when each of the cams is at a second angle.Type: ApplicationFiled: February 7, 2022Publication date: August 10, 2023Inventor: KUO-CHI LIN
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Patent number: 9574634Abstract: A damper includes a cylinder, cores and covers. The cylinder includes eccentric bores each confined in a wall formed with a thick portion and a thin portion located opposite to the thick portion. The thick portions of the eccentric bores are located on different sides of the cylinder. Each core is inserted in a corresponding eccentric bore. The covers close the eccentric bores to keep the cores in the eccentric bores. The cores are made with a volume smaller than that of the eccentric bores. The cores are separated from each other. The cores exert forces on the walls of the eccentric bores because of inertia to alleviate vibration of the cylinder.Type: GrantFiled: May 29, 2015Date of Patent: February 21, 2017Assignee: MONKULA ENTERPRISE CO., LTD.Inventor: Kuo-Chi Lin
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Publication number: 20160348746Abstract: A damper includes a cylinder, cores and covers. The cylinder includes eccentric bores each confined in a wall formed with a thick portion and a thin portion located opposite to the thick portion. The thick portions of the eccentric bores are located on different sides of the cylinder. Each core is inserted in a corresponding eccentric bore. The covers close the eccentric bores to keep the cores in the eccentric bores. The cores are made with a volume smaller than that of the eccentric bores. The cores are separated from each other. The cores exert forces on the walls of the eccentric bores because of inertia to alleviate vibration of the cylinder.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Inventor: Kuo-Chi LIN
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Patent number: 8541973Abstract: A single stage low boost/buck ratio stand-alone solar energy power generating circuit with a system thereof is a simplification of a two-stage type circuit. The two-stage circuit, which has a storage unit, a charging converter circuit for charging the storage unit, and a discharging converter circuit for discharging the stored power to a load, is analyzed and categorized such that a circuit structure is selected via a suitable simplified combination to commonly use the elements constituting the charging and the discharging converter circuits so as to form the single stage circuit with less elements, volume and weight for reducing the production cost of the circuit.Type: GrantFiled: November 22, 2009Date of Patent: September 24, 2013Assignee: Richtek Technology Corp.Inventors: Sheng-Yu Tseng, Ying-Jhih Wu, Kuo-Chi Lin
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Patent number: 8371776Abstract: A cutting tool includes a blade, a seat, a shank and a damper. The blade is connected to the seat. The seat is connected to the shank. The shank includes a pocket defined therein and a thread formed on the wall of the pocket. A damper is inserted in the pocket. The damper includes a thread formed on the periphery for engagement with the thread of the shank, with a small gap defined between the threads.Type: GrantFiled: November 17, 2009Date of Patent: February 12, 2013Assignee: Ying-Fan Enterprise Co., Ltd.Inventor: Kuo-Chi Lin
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Publication number: 20120305721Abstract: A multifunction peg comprises a main body and two second pressing arms. Each second pressing arm includes a through hole and two hooks. A through hole is formed at an upper part of the second pressing arm, and includes a large round hole, two middle round holes and two small holes, for fitting and receiving a salient or a nail. The multifunction peg can hold an article and versatilely engage with a salient or a nail prefixed to a wall or a wooden board, thereby getting fixed in position.Type: ApplicationFiled: June 6, 2011Publication date: December 6, 2012Inventor: Kuo-Chi LIN
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Patent number: 8292134Abstract: A multifunction clothes hanger includes a main body, a hook, an annular member and two clothes hangers. A protrusion of a cylindrical body of each clothes hanger enters a T-shaped through-groove at the bottom of the main body and moves into a transverse portion of the T-shaped through-groove to enter left and right through-holes of the main body. The protrusion is engaged with grooves disposed on the inner sides of the left and right through-holes, respectively. Furthermore, the hook is inserted into a straight through-hole at the upper portion of the main body until the threaded bottom with a thread thereon reaches the bottom of the main body to engage with a screw nut of the annular member. Another space-saving multifunction clothes hanger further includes a fixing base, upper and lower arms, two grooves, left and right baffles and two screw holes.Type: GrantFiled: December 3, 2010Date of Patent: October 23, 2012Inventor: Kuo-Chi Lin
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Publication number: 20120138640Abstract: A multifunction clothes hanger includes a main body, a hook, an annular member and two clothes hangers. A protrusion of a cylindrical body of each clothes hanger enters a T-shaped through-groove at the bottom of the main body and moves into a transverse portion of the T-shaped through-groove to enter left and right through-holes of the main body. The protrusion is engaged with grooves disposed on the inner sides of the left and right through-holes, respectively. Furthermore, the hook is inserted into a straight through-hole at the upper portion of the main body until the threaded bottom with a thread thereon reaches the bottom of the main body to engage with a screw nut of the annular member. Another space-saving multifunction clothes hanger further includes a fixing base, upper and lower arms, two grooves, left and right baffles and two screw holes.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Inventor: Kuo-Chi LIN
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Publication number: 20110116883Abstract: A cutting tool includes a blade, a seat, a shank and a damper. The blade is connected to the seat. The seat is connected to the shank. The shank includes a pocket defined therein and a thread formed on the wall of the pocket. A damper is inserted in the pocket. The damper includes a thread formed on the periphery for engagement with the thread of the shank, with a small gap defined between the threads.Type: ApplicationFiled: November 17, 2009Publication date: May 19, 2011Inventor: Kuo-Chi LIN
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Publication number: 20100322722Abstract: A combinative cutter includes a holder, a shank, a blade and at least two screws. The holder includes an eccentric bore defined at an end and at least two screw holes in communication with the eccentric bore. The shank is inserted in the eccentric bore and formed with a planar face. The blade is attached to an end of the shank extending beyond the holder. The screws are driven through the screw holes and abutted against the planar face to keep the shank in the eccentric bore.Type: ApplicationFiled: June 13, 2008Publication date: December 23, 2010Applicant: YING-FAN ENTERPRISE CO., LTD.Inventor: Kuo-Chi Lin
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Patent number: 6271086Abstract: A method for preventing the cluster defect of HSG is disclosed. Where the cluster defect means that when wafer with HSGs are cleaned just when HSGs are formed, there are a plurality of clusters appear on HSGs. In comparison with conventional fabrication that wafer and HSGs are directly cleaned just when these HSGs are formed. The idea behind the invention is that when HSGs are formed, a heat treatment is applied to change surface states of HSGs before wafer and HSGs are cleaned. Owing to the fact that these surface states of HSGs are improved by the heat treatment, no cluster will be formed during following clean process. Thus, the formation of cluster is obviously protected and then quality of any application of HSGs is improved by the invention.Type: GrantFiled: June 30, 1999Date of Patent: August 7, 2001Assignee: United Microelectronics Corp.Inventors: Kuo-Chi Lin, Da-Wen Hsia, Cheng-Chiech Huang
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Patent number: 6225160Abstract: A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.Type: GrantFiled: April 20, 1999Date of Patent: May 1, 2001Assignee: United Microelectronics, Corp.Inventors: Kuo-Chi Lin, Kuo-Tai Huang, Da-Wen Shia, Kun-Chi Lin
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Patent number: 6204107Abstract: A method for forming a multi-layered liner on the sidewalls of a node contact opening includes the steps of providing a substrate having a dielectric layer thereon. The dielectric layer further includes a node contact opening that exposes a portion of the substrate. A first liner layer is then formed on the sidewalls of the node contact opening. Next, a second liner layer is formed over the first liner layer such that the first liner layer and the second liner layer together form a dual-layered liner. The first liner layer in contact with the dielectric layer has good insulation capacity while the second liner layer has good etch-resisting property.Type: GrantFiled: December 8, 1998Date of Patent: March 20, 2001Assignee: United Microelectronics Corp.Inventors: Kuo-Chi Lin, Kuen-Yow Lin, Chien-Hua Tsai, Kun-Chi Lin
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Patent number: 6191042Abstract: A method of fabricating a node contact opening includes formation of a dielectric layer on a substrate. An opening is formed with C4F8/Ar/CH2F2 as an etchant. A portion of the dielectric layer under the opening is etched with CHF3/CO as an etchant until the substrate is exposed. A node contact opening is formed.Type: GrantFiled: February 8, 1999Date of Patent: February 20, 2001Assignee: United Microelectronics Corp.Inventors: Chien-Hua Tsai, Kuo-Chi Lin
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Patent number: 6177326Abstract: A method for fabricating a bottom electrode is provided. In this method a dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilicon layer is formed on the dielectric layer and fills the via hole, wherein the cross-section of the patterned doped polysilicon layer is arced or polygonal. The surface of the patterned polysilicon layer is transformed into an amorphous silicon layer. A hemispherical-grain layer is formed on the amorphous silicon layer.Type: GrantFiled: December 8, 1998Date of Patent: January 23, 2001Assignee: United Microelectronics Corp.Inventors: Yi-Tyng Wu, Kuo-Chi Lin
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Patent number: 6150216Abstract: A method for forming an electrode of semiconductor device capacitor is disclosed. The method comprises forming a dielectric layer on a semiconductor substrate and then using photolithographic method to etch a trench through the dielectric layer to expose specific part of the semiconductor substrate. A polysilicon layer is then formed over the dielectric layer and filled the trench. The polysilicon layer is patterned by a photoresist layer and etched back to the dielectric layer, then a polysilicon rod is formed. A spacer method is used to form an amorphized silicon spacer is sidewall of the polysilicon rod. The polysilicon rod is then implanted to form an amorphized polysilicon layer on top surface of the polysilicon rod. Final hemispherical grain silicon is formed on the spacer and the amorphized polysilicon layer to increase the surface area of the polysilicon rod. Thereby, an electrode of a semiconductor device capacitor is formed, and the capacitance of capacitor is enhanced.Type: GrantFiled: December 29, 1998Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Kuo-Chi Lin, Kun-Chi Lin
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Patent number: 6150215Abstract: A method for ensuring no capacitor peeling at the edge of a wafer in the fabrication of dynamic random access memory (DRAM) is disclosed. The method includes first providing a semiconductor substrate having a semiconductor structure formed thereon. A dielectric layer is then formed overlying the semiconductor structure, and patterned for defining a contact window. Followed by, the deposition of a silicon layer over the dielectric layer that fills up the contact window. Consequentially, a photoresist layer is coated overlying the silicon layer, where it will be rinsed twice by a combination of an online EBR (and/or a WEE) and an offline EBR at a distance inwardly away from the edge of the wafer in process for removing a portion of the photoresist to avoid abnormal capacitor formation in later stages. Then, a photolithography process is carried out against the photoresist layer to form a photoresist mask.Type: GrantFiled: August 10, 1999Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Kuo-Chi Lin, Da-Wen Hsia