Abstract: A wide-band gap semiconductor device and a method of manufacturing the same are provided. The wide-band gap semiconductor device of the disclosure includes a substrate, an epitaxial layer, an array of merged PN junction Schottky (MPS) diode, and an edge termination area surrounding the array of MPS diode. The epitaxial layer includes a first plane, a second plane, and trenches between the first plane and the second plane. The array of MPS diode is formed in the first plane of the epitaxial layer. The edge termination area includes a floating ring region having floating rings formed in the second plane of the epitaxial layer, and a transition region between the floating ring region and the array of MPS diode. The transition region includes a PIN diode formed in the plurality of trenches and on the epitaxial layer between the trenches.

Abstract: An electronic device and a temperature detection device thereof are provided. The temperature detection device includes a differential stage circuit and an output stage circuit. The differential stage circuit includes a first differential end and a second differential end, and includes a cross-coupled transistor element, a first resistor and a second transistor. The cross-coupled transistor element receives a first voltage. The first resistor is coupled between the first differential end and a second voltage, and the first resistor is poly-silicon resistor. The second resistor is coupled between the second differential end and the second voltage, and the second resistor is a silicon carbide diffusion resistor. The output stage circuit generates a driving voltage according to a first control voltage on the first differential end and a second control voltage on the second differential end.

Abstract: A temperature sensing device includes a resistor string and a control circuitry. The resistor string includes a variable resistor, a first resistor, and a second resistor which are coupled in series with each other. The resistor string is coupled between a sensing end and a reference ground voltage. The first resistor and the second resistor are coupled to a monitoring end to provide a monitoring voltage. The control circuitry compares the monitoring voltage with a plurality of reference voltages to generate sensing temperature information, and generate adjustment information according to the sensing temperature information. The control circuitry adjusts a resistance provided by the variable resistor according to the adjustment information. The first resistor is a polysilicon resistor, and the second resistor is a silicon carbide diffusion resistor.

Abstract: An electronic device and a temperature detection device thereof are provided. The temperature detection device includes a first resistor, a second resistor, and an operation circuit. The first resistor and the second resistor are coupled in series between a detection end and a first voltage. The first resistor and the second resistor divide a detection voltage on the detection end to generate a monitoring voltage. The operation circuit compares the monitoring voltage with a plurality of reference voltages to generate a plurality of comparison results. The operation circuit performs an operation on the comparison results to generate detection temperature information. The first resistor is a poly-silicon resistor and the second resistor is a silicon carbon (SiC) diffusion resistor.

Abstract: A driving voltage generating device includes a temperature detector, a controlling circuitry, a voltage generator, and an output stage circuitry. The temperature detector is coupled to a control terminal of a power transistor and is configured to generate temperature detection information by detecting an ambient temperature. The controlling circuitry is coupled to the temperature detector and generates an activation signal by determining whether the ambient temperature is abnormal according to the temperature detection information. The voltage generator generates an operation power according to the activation signal. The output stage circuitry is coupled to the voltage generator, generates a driving voltage according to the operation power, and provides the driving voltage to the control terminal of the power transistor.

Abstract: A silicon carbide semiconductor power transistor includes a silicon carbide substrate, a first drift layer, a second drift layer on the substrate with V-grooves, buried doped regions in the first drift layer below the V-grooves, gates in the V-grooves, a gate insulation layer, a delta doping layer, a well region, source regions, well pick-up regions, conductive trenches, and doping portions. Each of the buried doped regions is a predetermined distance from a bottom of each of the V-grooves. The delta doping layer is disposed in the second drift layer, and the V-grooves are across the delta doping layer. The conductive trenches are disposed in the second drift layer, and each of the conductive trenches passes through the well pick-up regions and contacts with the well region. The doping portions are respectively on sidewalls of the conductive trenches in the well region.

Abstract: A method of manufacturing a silicon carbide semiconductor power device is provided. In the method, the power device in high voltage (HV) region and CMOS device in the low voltage (LV) region are formed together, so the cost and time can be saved efficiently. First, a first drift layer is formed on a substrate, and then a shielding region is formed in the first drift layer. The shielding region includes a continuous region in the LV region. Then, a second drift layer is formed on the first drift layer. A pick-up region is formed in the second drift layer, wherein the pick-up region connects to the continuous region of the shielding region, and then NMOS and PMOS in the LV region and the power device in HV region are formed simultaneously. NMOS and PMOS are surrounded by the pick-up region and the continuous region, thereby minimizing body effect.

Abstract: A short-circuit protection circuitry is adapted for a power transistor. The short-circuit protection circuitry includes a first diode, a first resistor, a voltage dividing circuit, a gate voltage generator, a pull-down circuit, and a control signal generator. The first diode is coupled to a drain of the power transistor. The first resistor is coupled between the first diode and the power transistor. The voltage dividing circuit is coupled between a gate and a source of the power transistor to generate a dividing voltage. The gate voltage generator provides a gate voltage to the gate of the power transistor according to a first driving signal and a second driving signal. The pull-down circuit pulls down the gate voltage according to a control signal. The control signal generator generates the control signal according to the first driving signal, a voltage on the anode of the first diode and the dividing voltage.

Abstract: A semiconductor power device includes a substrate, a drift layer disposed on the substrate, buried doped regions, gates, a gate insulation layer, well regions, source regions, and well contact regions. The buried doped regions are in the drift layer and parallel to each other, and each of the buried doped regions is a predetermined distance from an upper surface of the drift layer. The gates are on the drift layer and directly above the buried doped regions. The gate insulation layer is between the drift layer and the gates. The well regions are in the drift layer between the gates and separated from the buried doped regions, wherein the well regions and the buried doped regions are electrically connected. The source regions are within the well regions between the gates, and each of the well contact regions passes through the source region and contacts with the well.

Abstract: A silicon carbide semiconductor power transistor includes a substrate made of SiC, a drift layer on a plane of the substrate, well regions in the drift layer, source regions within the well regions, gates on the drift layer, a gate insulation layer between the drift layer and each of the gates, and well pick-up regions in the drift layer. V-grooves are formed in the drift layer, and a bottom and sidewalls of each of the V-grooves is surround by each of the well regions. The bottom of each of the V-grooves is in direct contact with each of the source regions. The gates are between the V-grooves and extend to the sidewalls of the V-grooves on both sides thereof. The well pick-up regions are below the bottom of each of the V-grooves, and each of the well pick-up regions passes through the source regions and contacts with the well regions.

Abstract: A silicon carbide semiconductor power transistor and a method of manufacturing the same. The silicon carbide semiconductor power transistor of the disclosure includes a substrate made of silicon carbide (SiC), a drift layer disposed on the substrate, a gate layer formed on the drift layer, a plurality of first and second well pick-up regions disposed in the drift layer, a plurality of source electrodes, and a plurality of contacts. A plurality of V-grooves is formed in the drift layer. A first opening is formed in the gate layer at a bottom of each of the V-grooves, and a second opening is formed in the gate layer at a top of the drift layer between the V-grooves. The plurality of contacts is disposed inside the second opening to be in direct contact with the second well pick-up regions.

Abstract: A merged PiN Schottky (MPS) diode includes a substrate, a first epitaxial layer of a first conductivity type, doped regions of a second conductivity type, a second epitaxial layer of the first conductivity type, and a Schottky metal layer. The first epitaxial layer is disposed on the first surface of the substrate. The doped regions are disposed in a surface of the first epitaxial layer, wherein the doped regions consist of first portions and second portions, the first portions are electrically floating, and the second portions are electrically connected to a top metal. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein trenches are formed in the second epitaxial layer to expose the second portions of the doped regions. The Schottky metal layer is conformally deposited on the second epitaxial layer and the exposed second portions of the doped regions.

Abstract: A wide-band gap semiconductor device and a method of manufacturing the same are provided. The wide-band gap semiconductor device of the disclosure includes a substrate, an epitaxial layer, an array of merged PN junction Schottky (MPS) diode, and an edge termination area surrounding the array of MPS diode. The epitaxial layer includes a first plane, a second plane, and trenches between the first plane and the second plane. The array of MPS diode is formed in the first plane of the epitaxial layer. The edge termination area includes a floating ring region having floating rings formed in the second plane of the epitaxial layer, and a transition region between the floating ring region and the array of MPS diode. The transition region includes a PIN diode formed in the plurality of trenches and on the epitaxial layer between the trenches.