Abstract: A semiconductor device includes a substrate, a bottom electrode, a ferroelectric layer, a noble metal electrode, and a non-noble metal electrode. The bottom electrode is over the substrate. The ferroelectric layer is over the bottom electrode. The noble metal electrode is over the ferroelectric layer. The non-noble metal electrode is over the noble metal electrode.

Abstract: A semiconductor device includes a random access memory (RAM) structure and a dielectric layer. The RAM structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. The dielectric layer is over the substrate and laterally surrounds a lower portion of the RAM structure. From a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random access memory (FeRAM) device is over the substrate between the select gate and the first source/drain region. A transistor device is disposed on an upper surface of the substrate. The substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. The FeRAM device is arranged over the recessed surface.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a bottom electrode layer over a substrate; depositing a ferroelectric layer over the bottom electrode layer; depositing a first top electrode layer over the ferroelectric layer, wherein the first top electrode layer comprises a first metal; depositing a second top electrode layer over the first top electrode layer, wherein the second top electrode layer comprises a second metal, and a standard reduction potential of the first metal is greater than a standard reduction potential of the second metal; and removing portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer to form a memory stack, the memory stack comprising remaining portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer.

Abstract: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a memory cell on the semiconductor substrate, where the memory cell includes a bottom contact, a memory material on the bottom contact, a top contact on the memory material, a first electrical isolation structure laterally surrounding the top contact, and a second electrical isolation structure laterally surrounding the memory material and the bottom contact.

Abstract: A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A semiconductor device includes a semiconductor substrate, a memory gate, and a data storage element. The semiconductor substrate includes a memory well which has two source/drain regions and a channel region between the source/drain regions. The memory gate is disposed above the channel region. The data storage element includes a ferroelectric material, and is disposed around the memory gate to separate the memory gate from the channel region.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: The present disclosure relates to a ferroelectric memory device that includes a bottom electrode, a ferroelectric structure overlying the bottom electrode, and a top electrode overlying the ferroelectric structure where the bottom electrode includes molybdenum.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

Abstract: A semiconductor device includes a semiconductor substrate, a memory gate, and a data storage element. The semiconductor substrate includes a memory well which has two source/drain regions and a channel region between the source/drain regions. The memory gate is disposed above the channel region. The data storage element includes a ferroelectric material, and is disposed around the memory gate to separate the memory gate from the channel region.