Abstract: One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.

Abstract: A method includes forming a transistor over a substrate, the transistor comprising a channel region, a gate structure over the channel region, and a plurality of source/drain regions on opposite sides of the channel region; forming a source/drain contact over one of the source/drain regions; forming a source/drain via over the source/drain contact, wherein from a top view, the source/drain via has a T-shaped profile, the source/drain via has a first portion extending in a lengthwise direction of the channel region, and a second portion extending in a lengthwise direction of the gate structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.

Abstract: Semiconductor structures and method for manufacturing the same are provided. The method includes forming a first conductive structure over a substrate and forming a second conductive structure through a dielectric layer over the first conductive structure. The method further includes partially removing the dielectric layer to reduce a thickness of the dielectric layer along a first direction and forming a third conductive structure over the second conductive structure. In addition, a first portion of the third conductive structure is within a projection area of the second conductive structure along the first direction, and a second portion of the third conductive structure is outside the projection area of the second conductive structure along the first direction, and a first bottom surface of the first portion is spaced apart from a second bottom surface of the second portion by a distance along the first direction.

Abstract: Embodiments of the present disclosure relates to a semiconductor device structure. The structure includes a first source/drain feature, a first interlayer dielectric (ILD) disposed over the first source/drain feature, a first conductive feature extending through the first ILD and in electrical contact with the first source/drain feature, and a gate electrode layer extending through the first ILD and disposed adjacent the first conductive feature, wherein a top surface of the first conductive feature and a top surface of the gate electrode layer are substantially co-planar.

Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

Abstract: A semiconductor device includes a gate disposed over a substrate. A source/drain is disposed in the substrate. A conductive contact is disposed over the source/drain. An air spacer is disposed between the gate and the conductive contact. A first component is disposed over the gate. A second component is disposed over the air spacer. The second component is different from the first component.

Abstract: A semiconductor device includes a gate disposed over a substrate. A source/drain is disposed in the substrate. A conductive contact is disposed over the source/drain. An air spacer is disposed between the gate and the conductive contact. A first component is disposed over the gate. A second component is disposed over the air spacer. The second component is different from the first component.

Abstract: One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer, a gate dielectric layer covering two opposite sidewalls and a bottom of the gate electrode layer, and two gate spacers correspondingly covering portions of gate dielectric layer that covers the two opposite sidewalls of the gate electrode layer. The method also includes forming a contact structure adjacent to one of the two gate spacers, successively recessing the contact structure and the one of the two gate spacers to form a recess that exposes the contact structure and the one of the two gate spacers, and forming a first insulating capping feature in the recess to cover and a top of the contact structure.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes a first contact plug and a second contact plug through a first dielectric layer, forming a second dielectric layer over the first contact plug, the second contact plug and the first dielectric layer, etching the second dielectric layer to form a first opening exposing the first contact plug, the second contact plug and the first dielectric layer, forming a bottom via portion in the first opening, forming a third dielectric layer over the bottom via portion and the second dielectric layer, etching the third dielectric layer to form a second opening exposing the bottom via portion, and forming a top via portion in the second opening. The top via portion and the bottom via portion form a first via.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a first insulating capping feature formed over the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed adjacent to the gate electrode layer and a second insulating capping feature formed over the source/drain contact structure. The second insulating capping feature and the first insulating capping feature are made of different materials, and an air gap directly below and in direct contact with the second insulating capping feature.

Abstract: An exemplary semiconductor device includes a substrate, a first conductive feature, a second conductive feature, and a third conductive feature over the substrate. The first conductive feature has a first top surface and a side surface. The third conductive feature is on the first top surface of the first conductive feature and is spaced away from the second conductive feature. The third conductive feature has a first sidewall and a second sidewall opposing the first sidewall. The first sidewall extends between the first conductive feature and the second conductive feature. At least a segment of the first sidewall has a first slope. The second sidewall has a second slope. The second slope is greater than the first slope.

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a conductive structure. The method includes forming a first dielectric layer over the conductive structure. The method includes forming a conductive via structure that passes through the first dielectric layer. The conductive via structure is over and connected to the conductive structure, the conductive via structure has a first portion and a second portion over the first portion, and a first overall diffusion rate of the second portion in the first dielectric layer is lower than a second overall diffusion rate of the first portion in the first dielectric layer. The method includes forming a second dielectric layer over the conductive via structure and the first dielectric layer. The method includes forming a conductive line that passes through the second dielectric layer.

Abstract: An exemplary semiconductor device includes a substrate, a first conductive feature, a second conductive feature, and a third conductive feature over the substrate. The first conductive feature has a first top surface and a side surface. The third conductive feature is on the first top surface of the first conductive feature and is spaced away from the second conductive feature. The third conductive feature has a first sidewall and a second sidewall opposing the first sidewall. The first sidewall extends between the first conductive feature and the second conductive feature. At least a segment of the first sidewall has a first slope. The second sidewall has a second slope. The second slope is greater than the first slope.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a conductive capping feature formed on and in direct contact with the gate electrode layer. The semiconductor device structure includes a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer, and an air gap is adjacent to the S/D contact structure, and the air gap is lower than the conductive capping feature.