Patents by Inventor Kuo-Chieh Wang
Kuo-Chieh Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134155Abstract: An imaging optical lens assembly includes four lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one of all lens surfaces of the four lens elements is aspheric and has at least one inflection point.Type: ApplicationFiled: October 9, 2023Publication date: April 25, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Yu-Tai TSENG, Yu-Chun KE, Kuo-Jui WANG, Tzu-Chieh KUO
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Publication number: 20240112959Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
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Patent number: 11948973Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.Type: GrantFiled: August 16, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang
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Publication number: 20240105719Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin, Chih-Hao Wang
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Patent number: 11929413Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.Type: GrantFiled: July 22, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Chuan You, Huan-Chieh Su, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 11916155Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.Type: GrantFiled: May 21, 2021Date of Patent: February 27, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
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Patent number: 10275387Abstract: The present invention provides method and associated interface circuit for mitigating interference due to signaling of a bus between two electronic apparatuses. The method may include: via the bus mechanically compliant to a bus specification, communicating and transporting data at a nonstandard speed which is not compliant to the bus specification. The method may further include: before communicating and transporting data at the nonstandard speed, signaling via the bus at a standard speed to configure a speed switching from the standard speed to the nonstandard speed, with the standard speed compliant to the bus specification. For example, the bus specification may be USB specification, the standard speed may be 5 Gbps (SuperSpeed of USB 3.0 specification), and the nonstandard speed may be lower than the standard speed, e.g., 2.5 Gbps, which forms a spectrum notch at a frequency of wireless connection, e.g., 2.4 GHz of Wi-Fi.Type: GrantFiled: June 17, 2016Date of Patent: April 30, 2019Assignee: MEDIATEK INC.Inventors: Ming-Pei Chen, Chuing-Nien Tseng, Juei-Ting Sun, Kuo-Chieh Wang
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Publication number: 20170046302Abstract: The present invention provides method and associated interface circuit for mitigating interference due to signaling of a bus between two electronic apparatuses. The method may include: via the bus mechanically compliant to a bus specification, communicating and transporting data at a nonstandard speed which is not compliant to the bus specification. The method may further include: before communicating and transporting data at the nonstandard speed, signaling via the bus at a standard speed to configure a speed switching from the standard speed to the nonstandard speed, with the standard speed compliant to the bus specification. For example, the bus specification may be USB specification, the standard speed may be 5 Gbps (SuperSpeed of USB 3.0 specification), and the nonstandard speed may be lower than the standard speed, e.g., 2.5 Gbps, which forms a spectrum notch at a frequency of wireless connection, e.g., 2.4 GHz of Wi-Fi.Type: ApplicationFiled: June 17, 2016Publication date: February 16, 2017Inventors: Ming-Pei Chen, Chuing-Nien Tseng, Juei-Ting Sun, Kuo-Chieh Wang
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Publication number: 20140131362Abstract: The present invention relates to an improved and a novel pan handle for a pan. The pan comprises a pan body and a pan handle. The pan handle is disposed on the sidewall of the pan body, comprising a holding portion for a user to hold and a first projection portion disposed on the sidewall of the pan handle for the user's fingers to press against such that the user can move or turn the pan body angularly with the pan handle as the axis. When a user uses a pan according to the present invention, the user may hold the pan by means of the holding portion of the pan handle and exert force by pressing fingers against the first projection portion as a lever. As a result, the pan handle according to the present invention enables the user to exercise greater control of the pan and to exert less labor in handling the pan.Type: ApplicationFiled: January 25, 2013Publication date: May 15, 2014Applicant: Allure Home Creations Co., Inc.Inventors: Stanley Ho, Emmanuel Lin, Kuo-Chieh Wang