Patents by Inventor Kuo-Chien Wang

Kuo-Chien Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wire bond pad design for compact stacked-die package
    Patent number: 12051660
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: July 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • WIRE BOND PAD DESIGN FOR COMPACT STACKED-DIE PACKAGE
    Publication number: 20220052002
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • Wire bond pad design for compact stacked-die package
    Patent number: 11189582
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 30, 2021
    Assignee: Western Digital Technologies Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • WIRE BOND PAD DESIGN FOR COMPACT STACKED-DIE PACKAGE
    Publication number: 20210151399
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Application
    Filed: December 6, 2019
    Publication date: May 20, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu