Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body contact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.

Abstract: An embodiment of the invention shows a high-voltage MOS field-effect transistor connected in series with a Schottky diode. When the Schottky diode is forwardly biased, the high-voltage MOSFET can act as a switch and sustain a high drain-to-source voltage. When the Schottky diode is reversely biased, the Schottky diode can protect the integrate circuit where the high-voltage MOSFET is formed, because the integrate circuit might otherwise burn out due to an exceedingly-large reverse current.

Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.

Abstract: A high-voltage startup circuit in an integrated circuit with a high-voltage pin and an operating voltage pin is disclosed, capable of having both low standby power consumption and high-speed transient response. An ultra-high voltage transistor and a main NMOS transistor are connected in series via a joint node between the high-voltage pin and the operating voltage pin. A pull-up circuit controlled by a stop signal is connected between the joint node and a first gate of the main NMOS transistor. A pull-down circuit controlled by the stop signal is connected to the first gate of the main NMOS transistor. When the stop signal is de-asserted the pull-up circuit couples the joint node to the first gate. When the stop signal is asserted the pull-up circuit performs an open circuit and the pull-down circuit pulls down the first gate voltage.

Abstract: A high-voltage startup circuit in an integrated circuit with a high-voltage pin and an operating voltage pin is disclosed, capable of having both low standby power consumption and high-speed transient response. An ultra-high voltage transistor and a main NMOS transistor are connected in series via a joint node between the high-voltage pin and the operating voltage pin. A pull-up circuit controlled by a stop signal is connected between the joint node and a first gate of the main NMOS transistor. A pull-down circuit controlled by the stop signal is connected to the first gate of the main NMOS transistor. When the stop signal is de-asserted the pull-up circuit couples the joint node to the first gate. When the stop signal is asserted the pull-up circuit performs an open circuit and the pull-down circuit pulls down the first gate voltage.

Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.

Abstract: An embodiment of the invention shows a high-voltage MOS field-effect transistor connected in series with a Schottky diode. When the Schottky diode is forwardly biased, the high-voltage MOSFET can act as a switch and sustain a high drain-to-source voltage. When the Schottky diode is reversely biased, the Schottky diode can protect the integrate circuit where the high-voltage MOSFET is formed, because the integrate circuit might otherwise burn out due to an exceedingly-large reverse current.

Abstract: A constant current regulator includes a first transistor having a first terminal coupled with an input voltage; a second transistor having a first terminal coupled with a control terminal of the first transistor; a third transistor having a first terminal coupled with the first terminal of the first transistor and having a control terminal coupled with the first terminal of the second transistor; a first resistor having a first terminal coupled with a second terminal of the third transistor and having a second terminal coupled with a control terminal of the second transistor; a second resistor having a first terminal coupled with the control terminal of the second transistor and having a second terminal coupled with a second terminal of the second transistor; and a third resistor having a first terminal coupled with the second terminal of the third transistor and having a second terminal coupled with a fixed-voltage terminal.

Abstract: A driver circuit for driving an LED array is disclosed. The LED array includes a first, a second, a third, a fourth LED device and a diode device. The second LED device is connected to the first LED device. The fourth LED device is connected to the third LED device. The diode device is connected between the second LED device and the third LED device. The driver circuit includes a first constant current regulator for coupling between the first and the second LED device; a second constant current regulator for coupling between the second and the third LED device; a third constant current regulator for coupling between the third and the fourth LED device; a fourth constant current regulator for coupling between the fourth LED device and a fixed-voltage terminal; and a control circuit coupled with the first, the second, the third, and the fourth constant current regulators.

Abstract: A control circuit for an AC-DC power converter includes a junction field effect transistor (JFET), a first resistor, a second resistor, and a third resistor. The JFET includes a substrate, a drain, a source, a gate, a first oxide layer, and a second oxide layer. The first oxide layer is attached to a region located between the drain and the gate of the JFET, and the second oxide layer is not attached to a region located between the drain and the gate of the JFET. The first resistor is positioned on the first oxide layer, and the second resistor and the third resistor are positioned on the second oxide layer. When the JFET and the first resistor receive an input power signal, the first, the second, and the third resistors divide the input power signal, and prevent from the breakdown of the first oxide layer and the second oxide layer.