Patents by Inventor Kuo-Chin Liu

Kuo-Chin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055527
    Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Patent number: 11830948
    Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Publication number: 20230369334
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Duen-Huei Hou, Tsu Hao Wang, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu
  • Patent number: 11749681
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J. H. Wang
  • Publication number: 20230066097
    Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Han-Yu Tsai, Zu-Yin Liu, You-Ting Lin, Jiun-Ming Kuo, Kuo-Chin Liu
  • Publication number: 20210366909
    Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.
    Type: Application
    Filed: March 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Duen-Huei Hou, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu, J.H. Wang
  • Publication number: 20210257497
    Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.
    Type: Application
    Filed: September 14, 2020
    Publication date: August 19, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Patent number: 10131539
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Han Meng, Chih-Hsien Hsu, Chia-Chi Chung, Yu-Pei Chiang, Wen-Chih Chen, Chen-Huang Huang, Zhi-Sheng Xu, Jr-Sheng Chen, Kuo-Chin Liu, Lin-Ching Huang
  • Publication number: 20180148324
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.
    Type: Application
    Filed: October 5, 2017
    Publication date: May 31, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Han MENG, Chih-Hsien HSU, Chia-Chi CHUNG, Yu-Pei CHIANG, Wen-Chih CHEN, Chen-Huang HUANG, Zhi-Sheng XU, Jr-Sheng CHEN, Kuo-Chin LIU, Lin-Ching HUANG
  • Patent number: 7202170
    Abstract: A method of forming floating gates for flash memory devices. A plurality of substrates is provided, in which a film to be etched and an overlying masking pattern layer are provided overlying each substrate. Each of the films in a plasma chamber is etched in sequence using the masking pattern layer as an etch mask, a polymer layer being deposited over the inner wall of the plasma chamber during the etching. An intermediary cleaning process is performed in the plasma chamber between the etchings before the deposited polymer layer reaches such a degree as to induce lateral etching on the next film to be etched, thereby improving etching profile of the films.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: April 10, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chin Liu, Chung-Long Leu, Mei-Hou Ke
  • Publication number: 20050236366
    Abstract: A method of etching a polysilicon layer comprising the following steps. A polysilicon layer is formed over a structure and the polysilicon layer is etched using at least a C2F6 etching process to form an etched polysilicon layer having a vertical profile.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 27, 2005
    Inventor: Kuo-Chin Liu
  • Publication number: 20050158975
    Abstract: A method of forming floating gates for flash memory devices. A plurality of substrates is provided, in which a film to be etched and an overlying masking pattern layer are provided overlying each substrate. Each of the films in a plasma chamber is etched in sequence using the masking pattern layer as an etch mask, a polymer layer being deposited over the inner wall of the plasma chamber during the etching. An intermediary cleaning process is performed in the plasma chamber between the etchings before the deposited polymer layer reaches such a degree as to induce lateral etching on the next film to be etched, thereby improving etching profile of the films.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Kuo-Chin Liu, Chung-Long Leu, Mei-Hou Ke