Abstract: The present disclosure provides an electronic package and a method for fabricating the same. The method including: connecting a first carrier structure with an electronic component via a bonding layer formed thereon; stacking the first carrier structure on a second carrier structure via a plurality of conductive elements; and electrically connecting the electronic component to the second carrier structure to thereby maintain and secure the distance between the first and second carrier structures.

Abstract: A packaging substrate is provided, which includes: a laminated body; first, second and third conductive pads formed on a surface of the laminated body so as for conductive bumps to be respectively mounted thereon, wherein the third conductive pad is positioned outside of an area between projections of the conductive bumps on the first and second conductive pads on the surface of the laminated body; first, second and third conductive vias formed in the laminated body and electrically connected to the first, second and third conductive pads, respectively; and first, second and third internal conductive traces formed in the laminated body and electrically connected to the first, second and third conductive vias, respectively, thereby preventing bridging from occurring between the conductive bumps and the conductive traces and overcoming non-wetting of the conductive bumps caused by a solder mask layer.

Abstract: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.

Abstract: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.

Abstract: An electronic carrier board for a chip to be mounted thereon is provided, which includes a body and a plurality of solder pads. The solder pads have carrying surfaces for carrying the chip thereon through conductive bumps. The carrying surfaces of at least two solder pads are oppositely inclined with respect to each other, thereby preventing the conductive bumps mounted on the carrying surfaces from displacement and thereby further preventing two adjacent conductive bumps subject to displacement from coming into short-circuit contact.

Abstract: An electronic carrier board for a chip to be mounted thereon is provided, which includes a body and a plurality of solder pads. The solder pads have carrying surfaces for carrying the chip thereon through conductive bumps. The carrying surfaces of at least two solder pads are oppositely inclined with respect to each other, thereby preventing the conductive bumps mounted on the carrying surfaces from displacement and thereby further preventing two adjacent conductive bumps subject to displacement from coming into short-circuit contact.

Abstract: A flip-chip semiconductor package structure and a package substrate applicable thereto are disclosed. The package substrate includes a body having at least a chip-attach area disposed thereon; a plurality of solder pads disposed in the chip-attach area and arranged at different intervals; and a fluid-disturbing portion disposed in the chip-attach area at a position where the solder pads are loosely arranged. A flip-chip semiconductor chip is mounted on the solder pads via conductive bumps and an underfill material is filled between the package substrate and the flip-chip semiconductor chip, the underfill material encapsulating the conductive bumps and the fluid-disturbing portion.

Abstract: A semiconductor device having at least an electronic component and its fabrication method are disclosed. The fabrication method comprises: applying a conductive material on each one of at least a paired solder pads arranged on a substrate by screen printing, with a recess formed in the conductive material on each one of the at least a paired solder pads, so as to expose a portion of each one of the at least a paired solder pads, wherein the recesses on the at least a paired solder pads are formed in position corresponding to each other; and mounting at least an electronic component having two opposing conductive terminals on the at least a paired solder pads, in a manner that the two opposing conductive terminals are introduced into the corresponding recesses of the conductive material so as for the electronic component to be electrically connected to the at least a paired solder pads via the conductive material by reflow.