Patents by Inventor Kuo-Ching Yang

Kuo-Ching Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120405
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Heng-Ching Lin, Yu-Teng Tseng, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 9299796
    Abstract: A method for manufacturing a metal-oxide-semiconductor (MOS) gate stack structure in an insta-MOS field-effect-transistor (i-MOSFET) includes the following steps of: forming a silicon nitride layer over a silicon substrate; forming a nanopillar structure including a silicon-germanium alloy layer in contact with the silicon nitride layer; and performing a thermal oxidation process on the nanopillar structure to cause germanium atoms in the silicon-germanium alloy layer to penetrate the underneath silicon nitride layer to form a silicon-germanium shell layer in contact with the silicon substrate and a germanium nanosphere located over the silicon germanium shell layer, and to form a separating layer between the silicon-germanium shell layer and the germanium nanosphere by oxidizing silicon atoms from the silicon nitride layer or the silicon substrate, thereby forming a germanium/silicon dioxide/silicon-germanium i-MOS gate stack structure capable of solving interfacial issues between silicon and germanium and b
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: March 29, 2016
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventors: Pei-Wen Li, Wei-Ting Lai, Ting-Chia Hsu, Kuo-Ching Yang, Po-Hsiang Liao, Thomas George
  • Publication number: 20160013283
    Abstract: A method for manufacturing a metal-oxide-semiconductor (MOS) gate stack structure in an insta-MOS field-effect-transistor (i-MOSFET) includes the following steps of: forming a silicon nitride layer over a silicon substrate; forming a nanopillar structure including a silicon-germanium alloy layer in contact with the silicon nitride layer; and performing a thermal oxidation process on the nanopillar structure to cause germanium atoms in the silicon-germanium alloy layer to penetrate the underneath silicon nitride layer to form a silicon-germanium shell layer in contact with the silicon substrate and a germanium nanosphere located over the silicon germanium shell layer, and to form a separating layer between the silicon-germanium shell layer and the germanium nanosphere by oxidizing silicon atoms from the silicon nitride layer or the silicon substrate, thereby forming a germanium/silicon dioxide/silicon-germanium i-MOS gate stack structure capable of solving interfacial issues between silicon and germanium and b
    Type: Application
    Filed: February 11, 2015
    Publication date: January 14, 2016
    Inventors: Pei-Wen Li, Wei-Ting Lai, Ting-Chia Hsu, Kuo-Ching Yang, Po-Hsiang Liao, Thomas George