Patents by Inventor Kuo-Chu Chiang

Kuo-Chu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12122123
    Abstract: A composite material structure, including an outer layer, an inner layer, and a middle layer, is provided. The outer layer includes a metallic material. The inner layer includes a fiber material and a resin material. The outer layer has a first thickness, the inner layer has a second thickness, and the first thickness is different from the second thickness. The middle layer includes an adhesive material and is disposed between the outer layer and the inner layer. Two opposite surfaces of the middle layer are respectively in direct contact with the outer layer and the inner layer. A manufacturing method of the composite material structure is also provided.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: October 22, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Han-Ching Huang, Sheng-Hung Lee, Jung-Chin Wu, Kuo-Nan Ling, Chih-Wen Chiang, Chien-Chu Chen
  • Patent number: 6818538
    Abstract: A ball grid array semiconductor packaging technology is provided, which is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: November 16, 2004
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Kuo-Chu Chiang, Yu-Ting Lai, Chin Te Chen
  • Publication number: 20040169273
    Abstract: A ball grid array semiconductor packaging technology is provided, which is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.
    Type: Application
    Filed: April 18, 2003
    Publication date: September 2, 2004
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Kuo-Chu Chiang, Yu-Ting Lai, Chin Te Chen