Patents by Inventor Kuo-Chuan Liu

Kuo-Chuan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240274675
    Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs). A substrate includes fin-like protruding portions in which source/drain regions are formed on the fin-like protruding portions of the substrate. The source/drain regions are laterally adjacent and electrically coupled to the nanostructure channels. A dielectric material is partially filling spaces between the fin-like protruding portions and partially are coupled to the source/drain regions. A barrier layer is on the dielectric material and covers portions of the source/drain regions. A source/drain contact is formed in the barrier layer and is partially in contact with the source/drain regions. The barrier layer and the dielectric material that formed below the MD contact in spaces between the source/drain regions result in a reduction of parasitic capacitance of the metal contacts such as gate-drain capacitance (Cgd).
    Type: Application
    Filed: February 13, 2023
    Publication date: August 15, 2024
    Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Yu-Chun LIU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11764169
    Abstract: A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Patent number: 11579190
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Publication number: 20220283221
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
  • Publication number: 20220262746
    Abstract: A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chih YEW, Fu-Jen LI, Po-Yao LIN, Kuo-Chuan LIU
  • Patent number: 11340291
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Patent number: 11329006
    Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Publication number: 20200326370
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
  • Publication number: 20200312790
    Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chih YEW, Fu-Jen LI, Po-Yao LIN, Kuo-Chuan LIU
  • Patent number: 10698026
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Patent number: 10685920
    Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Publication number: 20180372796
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
  • Patent number: 10163862
    Abstract: A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Kuo-Chuan Liu
  • Patent number: 10067181
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Patent number: 10008480
    Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Publication number: 20180082961
    Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chih YEW, Fu-Jen LI, Po-Yao LIN, Kuo-Chuan LIU
  • Publication number: 20180026014
    Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Patent number: 9831190
    Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Patent number: 9780076
    Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Publication number: 20170248652
    Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
    Type: Application
    Filed: May 12, 2017
    Publication date: August 31, 2017
    Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN