Patents by Inventor Kuo-Chuan Liu
Kuo-Chuan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240274675Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs). A substrate includes fin-like protruding portions in which source/drain regions are formed on the fin-like protruding portions of the substrate. The source/drain regions are laterally adjacent and electrically coupled to the nanostructure channels. A dielectric material is partially filling spaces between the fin-like protruding portions and partially are coupled to the source/drain regions. A barrier layer is on the dielectric material and covers portions of the source/drain regions. A source/drain contact is formed in the barrier layer and is partially in contact with the source/drain regions. The barrier layer and the dielectric material that formed below the MD contact in spaces between the source/drain regions result in a reduction of parasitic capacitance of the metal contacts such as gate-drain capacitance (Cgd).Type: ApplicationFiled: February 13, 2023Publication date: August 15, 2024Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Yu-Chun LIU, Kuo-Cheng CHIANG, Chih-Hao WANG
-
Patent number: 11764169Abstract: A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer.Type: GrantFiled: May 9, 2022Date of Patent: September 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
-
Patent number: 11579190Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: GrantFiled: May 23, 2022Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
-
Publication number: 20220283221Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
-
Publication number: 20220262746Abstract: A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chih YEW, Fu-Jen LI, Po-Yao LIN, Kuo-Chuan LIU
-
Patent number: 11340291Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: GrantFiled: June 25, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
-
Patent number: 11329006Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.Type: GrantFiled: June 12, 2020Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
-
Publication number: 20200326370Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
-
Publication number: 20200312790Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.Type: ApplicationFiled: June 12, 2020Publication date: October 1, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chih YEW, Fu-Jen LI, Po-Yao LIN, Kuo-Chuan LIU
-
Patent number: 10698026Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: GrantFiled: August 31, 2018Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
-
Patent number: 10685920Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.Type: GrantFiled: November 27, 2017Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
-
Publication number: 20180372796Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: ApplicationFiled: August 31, 2018Publication date: December 27, 2018Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
-
Patent number: 10163862Abstract: A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.Type: GrantFiled: December 9, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Kuo-Chuan Liu
-
Patent number: 10067181Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: GrantFiled: May 12, 2017Date of Patent: September 4, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
-
Patent number: 10008480Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.Type: GrantFiled: October 2, 2017Date of Patent: June 26, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
-
Publication number: 20180082961Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.Type: ApplicationFiled: November 27, 2017Publication date: March 22, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chih YEW, Fu-Jen LI, Po-Yao LIN, Kuo-Chuan LIU
-
Publication number: 20180026014Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.Type: ApplicationFiled: October 2, 2017Publication date: January 25, 2018Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
-
Patent number: 9831190Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.Type: GrantFiled: January 9, 2014Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
-
Patent number: 9780076Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.Type: GrantFiled: November 18, 2016Date of Patent: October 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
-
Publication number: 20170248652Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: ApplicationFiled: May 12, 2017Publication date: August 31, 2017Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN