Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: When a ramp signal intersects a feedback related signal, a constant time switching regulator enters a first state and maintains in the first state for a constant time, and after the constant time ends, when the ramp signal exceeds the feedback related signal, the switching regulator enters a second state, while when the ramp signal does not exceed the feedback related signal, the switching regulator enters a third state. In the first state, the first end of an inductor is connected to input voltage and the second end of the inductor is connected to output voltage; in the second state, the first end is connected to ground and the second end is connected to output voltage; and in the third state, the first end is connected to input voltage and the second end is connected to ground.

Abstract: When a ramp signal intersects a feedback related signal, a constant time switching regulator enters a first state and maintains in the first state for a constant time, and after the constant time ends, when the ramp signal exceeds the feedback related signal, the switching regulator enters a second state, while when the ramp signal does not exceed the feedback related signal, the switching regulator enters a third state. In the first state, the first end of an inductor is connected to input voltage and the second end of the inductor is connected to output voltage; in the second state, the first end is connected to ground and the second end is connected to output voltage; and in the third state, the first end is connected to input voltage and the second end is connected to ground.

Abstract: A dual constant time switching regulator includes: a power circuit including an inductor and at least a power switch for converting an input power to an output power, and a switching control circuit for generating a switch control signal to control the power switch, wherein the switching control circuit includes a comparison circuit for comparing an error amplified signal and a triangle wave signal to generate a comparison result, and a time determining circuit for generating the switch control signal according to the comparison result, wherein after the power switch turns ON, it keeps ON for at least a minimum ON time until the triangle wave signal is higher than the error amplified signal, and wherein after the power switch turns OFF, it keeps OFF for at least a minimum OFF time and until the triangle wave signal is lower than the error amplified signal.

Abstract: A chemical mechanical polishing (CMP) method is disclosed in which a new polishing pad is broken-in and conditioned into a steady operating state while using a silica (SiO2) based CMP slurry and where the broken-in and conditioned pad is afterwards used for polishing patterned workpieces (e.g., semiconductor wafers) with a ceria (CeO2) based CMP slurry. The approach shortens break-in time and appears to eliminate a first wafer effect usually seen following break-in with ceria-based CMP slurries.

Abstract: A chemical mechanical polishing (CMP) method is disclosed in which a torque-based end-point algorithm is used to determine when polishing should be stopped. The end-point algorithm is applicable to situations where a ceria (CeO2) based CMP slurry is used for further polishing, pre-patterned and pre-polished workpieces (e.g., semiconductor wafers) which have a high friction over-layer (e.g., HDP-oxide) and a comparatively, lower friction and underlying layer of sacrificial pads (e.g., silicon nitride pads). A mass production wise, reliable and consistent signature point in the friction versus time waveform of a torque-representing signal is found and used to trigger an empirically specified duration of overpolish. A database may be used to define the overpolish time as a function of one or more relevant parameters.

Abstract: A chemical mechanical polishing method is disclosed in which a batch of wafers is first supplied to a low-selectivity, first CMP tool for partly polishing the batch with one or more relatively non-selective CMP slurries (e.g., silica (SiO2) based); and in which the batch of partly-polished wafers is subsequently transferred to a higher-selectivity, second CMP tool which uses one or more comparatively more-selective CMP slurries (e.g., ceria (CeO2) based) to further the polishing of the batch of partly-polished wafers and/or to complete the polishing of the partly-polished wafers.

Abstract: A chemical mechanical polishing (CMP) method is disclosed in which a torque-based end-point algorithm is used to determine when polishing should be stopped. The end-point algorithm is applicable to situations where a ceria (CeO2) based CMP slurry is used for further polishing, pre-patterned and pre-polished workpieces (e.g., semiconductor wafers) which have a high friction over-layer (e.g., HDP-oxide) and a comparatively, lower friction and underlying layer of sacrificial pads (e.g., silicon nitride pads). A mass production wise, reliable and consistent signature point in the friction versus time waveform of a torque-representing signal is found and used to trigger an empirically specified duration of overpolish. A database may be used to define the overpolish time as a function of one or more relevant parameters.

Abstract: A chemical mechanical polishing (CMP) method is disclosed in which a new polishing pad is broken-in and conditioned into a steady operating state while using a silica (SiO2) based CMP slurry and where the broken-in and conditioned pad is afterwards used for polishing patterned workpieces (e.g., semiconductor wafers) with a ceria (CeO2) based CMP slurry. The approach shortens break-in time and appears to eliminate a first wafer effect usually seen following break-in with ceria-based CMP slurries.

Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.

Abstract: A chemical mechanical polishing method is disclosed in which a batch of wafers is first supplied to a low-selectivity, first CMP tool for partly polishing the batch with one or more relatively non-selective CMP slurries (e.g., silica (SiO2) based); and in which the batch of partly-polished wafers is subsequently transferred to a higher-selectivity, second CMP tool which uses one or more comparatively more-selective CMP slurries (e.g., ceria (CeO2) based) to further the polishing of the batch of partly-polished wafers and/or to complete the polishing of the partly-polished wafers.

Abstract: In a polishing process (e.g. CMP), the endpoint is declared after (a) detecting that the friction between the polishing tool and the structure being polished is rising, then (b) determining that the friction is falling, then (c) waiting for a predetermined period of time (which can be zero). This algorithm results in reduced over-polishing in some embodiments. Other embodiments are also described.

Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: In a polishing process (e.g. CMP), the endpoint is declared after (a) detecting that the friction between the polishing tool and the structure being polished is rising, then (b) determining that the friction is falling, then (c) waiting for a predetermined period of time (which can be zero). This algorithm results in reduced over-polishing in some embodiments. Other embodiments are also described.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: To form substrate isolation for a nonvolatile memory, floating gate polysilicon (410) is formed over a semiconductor substrate (110), then silicon nitride (130) is deposited, and then the nitride, the floating gate polysilicon and the substrate are etched to form isolation trenches (140). Dielectric (150) is formed in the trenches and over the silicon nitride. The dielectric thickness is relatively small so that the top surface (150T) of the dielectric over the trenches lies at all times below the top surface of silicon nitride. The dielectric deposition and polishing times are therefore reduced. Other embodiments are also provided.

Abstract: A semiconductor processing system includes a semiconductor processing chamber constructed of a main body, a window support member, and a window. The window support member is located over an opening into the main body. The window is located over the window support component. At least one radiation passage is formed in the window support component. The radiation passage has a first end which is open to the internal dimensions of the main body and a second end, opposing the first end, which terminates against the window.