Patents by Inventor Kuo-Chun Yang

Kuo-Chun Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164051
    Abstract: A fan module is adapted to be disposed on a mainboard. The fan module includes a base, a stator unit, a circuit board, a first restriction structure and a second restriction structure. The base includes a mounting shaft and a base opening, wherein the mounting shaft has an axis. The mounting shaft is telescoped in the stator unit. The circuit board is coupled to the stator unit, wherein the circuit board includes a circuit board connection port. The first restriction structure restricts the circuit board, wherein the first restriction structure is arranged on the first straight line, and the first restriction structure is disposed a first distance away from the axis. The second restriction structure restricts the circuit board, wherein the second restriction structure is arranged on the second straight line, the second restriction structure is disposed a second distance away from the axis.
    Type: Application
    Filed: June 12, 2023
    Publication date: May 16, 2024
    Inventors: Kuo-Tung HSU, Wen-Chun HSU, Chao-Fu YANG, Shuo-Sheng HSU
  • Publication number: 20240162093
    Abstract: A method for fabricating semiconductor device includes first providing a substrate having a core region, a LNA region, a I/O region, and a PA region, forming a first gate structure on the LNA region, a second gate structure on the PA region, a third gate structure on the core region, and a fourth gate structure on the I/O region, forming an interlayer dielectric (ILD) layer on the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and then forming a first hard mask on the first gate structure and a second hard mask on the second gate structure. Preferably, a width of the first hard mask is greater than a width of the first gate structure.
    Type: Application
    Filed: December 13, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Chun Chang, Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Publication number: 20240128178
    Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
  • Publication number: 20240120405
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Heng-Ching Lin, Yu-Teng Tseng, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 11937415
    Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
  • Patent number: 10126954
    Abstract: A chipset implemented in a server node of a server system and including an embedded management controller (eMC) is disclosed. The eMC collects inner-node information of the server node for server system management. The eMC is coupled to a baseboard management controller (BMC) that is outside the server node and communicates with a remote console through a network. The eMC is specially designed for the corresponding server node to be differentiated from the other server nodes also coupled to the BMC. All eMCs coupled to the same BMC boot in a special way.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 13, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Shuang-Shuang Qin, Kuo-Chun Yang, Hao-Lin Lin
  • Patent number: 10101919
    Abstract: A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a baseboard management controller, and the baseboard management controller is outside the server node and communicates with a remote console through network.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 16, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Shuang-Shuang Qin, Kuo-Chun Yang, Hao-Lin Lin
  • Publication number: 20170139592
    Abstract: A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a baseboard management controller, and the baseboard management controller is outside the server node and communicates with a remote console through network.
    Type: Application
    Filed: November 30, 2015
    Publication date: May 18, 2017
    Inventors: Shuang-Shuang QIN, Kuo-Chun YANG, Hao-Lin LIN
  • Publication number: 20020084552
    Abstract: A method for manufacturing rubber plate having colored patterns thereon includes step 1: to prepare a heat transfer decal having a colored pattern thereon; step 2: to prepare a male mold and a rubber plate put on the male mold, the decal put on the rubber plate; step 3: to prepare a female mold having a recess defined therein, and step 5: to press the decal on the rubber plate between the male mold and the female mold at a high temperature. The pattern on the decal is printed on the rubber plate.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventor: Kuo-Chun Yang