Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.

Abstract: A semiconductor structure includes a plurality of devices, a molding disposed between the plurality of devices, and a RDL. Each of the plurality of devices includes a first surface disposed with a conductive structure. The molding includes a first surface coupled to the first surfaces of the plurality of devices. The RDL is disposed on the first surfaces of the plurality of devices and the first surface of the molding. The RDL includes a first portion directly over the first surface of the molding, a second portion directly over the first surfaces of the plurality of devices. A thickness of the first portion is greater than a thickness of the second portion.

Abstract: Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.

Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.

Abstract: A method of manufacturing a package structure is provided with the following steps, providing a first die, a second die and a third die; forming a first redistribution layer located on and electrically coupled to the first die, the second die and the third die; and forming an antenna located on and electrically coupled to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna.

Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

Abstract: A method of manufacturing a semiconductor structure includes disposing a plurality of devices on a carrier; immersing the plurality of devices into a molding compound to dispose the molding compound between the plurality of devices; and removing the carrier from the plurality of devices and the molding compound, wherein a first surface of the molding compound adjacent to a plurality of active components over the plurality of devices includes a recessed portion recessed from one of first surfaces of the plurality of devices.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a first polymer material layer, a second polymer material layer and a first redistribution layer. The encapsulant encapsulates sidewalls of the die. The first polymer material layer is on the encapsulant and the die. The second polymer material layer is on the first polymer material layer. The first redistribution layer is embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die. The first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer.

Abstract: A method includes placing a first plurality of dies over a carrier. The first plurality of dies include at least a first logic die and a first memory die, placing a second plurality of dies over the first plurality of dies. The second plurality of dies are electrically coupled to the first plurality of dies, and include at least a second logic die and a second memory die. A third plurality of dies are placed over the second plurality of dies, and are electrically coupled to the first plurality of dies and the second plurality of dies. The third plurality of dies include at least a third logic die and a third memory die. The method further includes forming electrical connectors over and electrically coupling to the first plurality of dies, the second plurality of dies, and the third plurality of dies.

Abstract: A semiconductor device includes a chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface, a back surface opposite to the active surface, and a thermal enhancement pattern on the back surface; and a heat dissipation structure connected to the chip package, the heat dissipation structure comprising a heat spreader having a flow channel for a cooling liquid, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern.

Abstract: Package structures and methods of forming the same are disclosed. The package structure includes a package, a device and a screw. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device is disposed over the package, wherein the dies and the encapsulant are disposed between the device and the redistribution structure. The screw penetrates through the package and the device.

Abstract: A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer.

Abstract: Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.

Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip attached to a first substrate and a thermal conductivity layer attached to the first chip. A molding compound encapsulates the chip and the thermal conductivity layer. Electrical connectors are arranged between the first substrate and a board. The molding compound covers upper surfaces of the thermal conductivity layer facing away from the electrical connectors.

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.