Patents by Inventor Kuo-Chung Yu
Kuo-Chung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961789Abstract: A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.Type: GrantFiled: October 20, 2020Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
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Publication number: 20240096825Abstract: A bond head is provided. The bond head includes a bond base, a chuck member, and an elastic material. The chuck member protrudes from a surface of the bond base, and has a chuck surface formed with vacuum holes for holding a die using differential air pressure. In the direction parallel to the chuck surface, the width of the chuck surface is less than the width of the bond base and is equal to or greater than the width of the die. The elastic material is disposed over the chuck surface. The elastic material is arranged around the periphery of the chuck surface to cover edges and/or corners of the chuck surface.Type: ApplicationFiled: February 8, 2023Publication date: March 21, 2024Inventors: Chen-Hua YU, Chih-Hang TUNG, Kuo-Chung YEE, Yian-Liang KUO, Jiun-Yi WU
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Publication number: 20240096760Abstract: A semiconductor package includes a chip, a redistribution structure, and first under- ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
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Publication number: 20240088077Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Chen-Hua Yu, Kuo-Chung Yee
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Publication number: 20240087986Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
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Patent number: 11929345Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.Type: GrantFiled: September 8, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun Hui Yu, Kuo-Chung Yee
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Patent number: 11916028Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant and a RDL structure, the encapsulant encapsulate sidewalls of the die. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.Type: GrantFiled: July 19, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
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Publication number: 20230375482Abstract: A semiconductor apparatus includes a transfer chamber, an annealing station, a robot arm, an edge detector and a trigger device. The transfer chamber is configured to interface with an electroplating apparatus. The robot arm is arranged to transfer a wafer from the transfer chamber to the annealing station. The edge detector, disposed over a predetermined location between the transfer chamber and the annealing station, comprises a first charge-coupled device (CCD) sensor and a second CCD sensor. When the robot arm is carrying the wafer to pass through the predetermined location, the first CCD sensor and the second CCD sensor are located over a first portion and a second portion of the edge bevel removal area respectively, and the trigger device is configured to activate the first CCD sensor and the second CCD sensor to capture an image of the first portion and an image of the second portion respectively.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Inventors: CHAO-TUNG WU, KUO-CHUNG YU, CHUNG-HAO HU, SHENG-PING WENG
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Patent number: 11781995Abstract: A semiconductor apparatus includes a transfer chamber, an annealing station, a robot arm, an edge detector and a trigger device. The transfer chamber is configured to interface with an electroplating apparatus. The robot arm is arranged to transfer a wafer from the transfer chamber to the annealing station. The edge detector, disposed over a predetermined location between the transfer chamber and the annealing station, comprises a first charge-coupled device (CCD) sensor and a second CCD sensor. When the robot arm is carrying the wafer to pass through the predetermined location, the first CCD sensor and the second CCD sensor are located over a first portion and a second portion of the edge bevel removal area respectively, and the trigger device is configured to activate the first CCD sensor and the second CCD sensor to capture an image of the first portion and an image of the second portion respectively.Type: GrantFiled: March 3, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chao-Tung Wu, Kuo-Chung Yu, Chung-Hao Hu, Sheng-Ping Weng
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Publication number: 20220187216Abstract: A semiconductor apparatus includes a transfer chamber, an annealing station, a robot arm, an edge detector and a trigger device. The transfer chamber is configured to interface with an electroplating apparatus. The robot arm is arranged to transfer a wafer from the transfer chamber to the annealing station. The edge detector, disposed over a predetermined location between the transfer chamber and the annealing station, comprises a first charge-coupled device (CCD) sensor and a second CCD sensor. When the robot arm is carrying the wafer to pass through the predetermined location, the first CCD sensor and the second CCD sensor are located over a first portion and a second portion of the edge bevel removal area respectively, and the trigger device is configured to activate the first CCD sensor and the second CCD sensor to capture an image of the first portion and an image of the second portion respectively.Type: ApplicationFiled: March 3, 2022Publication date: June 16, 2022Inventors: CHAO-TUNG WU, KUO-CHUNG YU, CHUNG-HAO HU, SHENG-PING WENG
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Patent number: 11268913Abstract: A method for inspecting a wafer includes: transferring the wafer from a transfer chamber to an annealing station by a robot arm; and monitoring at least one portion of an edge bevel removal area of the wafer over the robot arm when the wafer is transferred from the transfer chamber to the annealing station. The at least one portion of the edge bevel removal area includes a first portion and a second portion different from the first portion. When the wafer is passing through a predetermined location between the transfer chamber and the annealing station, a first charge-coupled device sensor located over the first portion of the edge bevel removal area is used to capture an image of the first portion, and a second charge-coupled device sensor located over the second portion of the edge bevel removal area is used to capture an image of the second portion.Type: GrantFiled: May 6, 2020Date of Patent: March 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chao-Tung Wu, Kuo-Chung Yu, Chung-Hao Hu, Sheng-Ping Weng
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Publication number: 20210334701Abstract: A machine learning method is provided, including: obtaining training data, where the training data includes a training feature, training labels, and a training weight; inputting the training data to a first machine learning model, where the first machine learning model has first model data, the first model data includes a first model feature, first model labels, and first model weights, and the first model labels correspond to the first model weights in a one-to-one manner; and training the first machine learning model by using a training step to obtain a second machine learning model. The training step includes: when the first model feature matches the training feature, and one of the first model labels is the same as any of the training labels, adjusting the first model weight corresponding to the first model label that is the same as any of the training labels according to the training weight.Type: ApplicationFiled: October 20, 2020Publication date: October 28, 2021Applicant: Tamkang UniversityInventors: Chih-Yung Chang, Shih-Jung Wu, Kuo-Chung Yu, Li-Pang Lu, Chia-Chun Wu
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Publication number: 20210256456Abstract: A work log posting system includes a project database, a meeting record analysis module, a project classification module, and a work log module. The project database stores a plurality of keyword sets, each corresponding to a project. The meeting record analysis module analyzes a meeting record including a statement content, an attendance list, and a meeting period, to extract a plurality of terms from the statement content of the meeting record. The project classification module classifies the meeting record to one of the projects according to the relevance between the terms in the statement content and each keyword set. The work log module counts, according to the classification result of the meeting record, the meeting period attended by each person on the attendance list and the project to which the meeting period belongs, so as to preload the statistical result into a work log.Type: ApplicationFiled: June 25, 2020Publication date: August 19, 2021Applicant: Tamkang UniversityInventors: Chih-Yung Chang, Shih-Jung Wu, Kuo-Chung Yu, Li-Pang Lu, Chia-Chun Wu
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Publication number: 20200264112Abstract: A method for inspecting a wafer includes: transferring the wafer from a transfer chamber to an annealing station by a robot arm; and monitoring at least one portion of an edge bevel removal area of the wafer over the robot arm when the wafer is transferred from the transfer chamber to the annealing station. The at least one portion of the edge bevel removal area includes a first portion and a second portion different from the first portion. When the wafer is passing through a predetermined location between the transfer chamber and the annealing station, a first charge-coupled device sensor located over the first portion of the edge bevel removal area is used to capture an image of the first portion, and a second charge-coupled device sensor located over the second portion of the edge bevel removal area is used to capture an image of the second portion.Type: ApplicationFiled: May 6, 2020Publication date: August 20, 2020Inventors: CHAO-TUNG WU, KUO-CHUNG YU, CHUNG-HAO HU, SHENG-PING WENG
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Patent number: 10648927Abstract: A semiconductor apparatus includes a transfer chamber, an annealing station, a robot arm, and an edge detector. The transfer chamber is configured to interface with an electroplating apparatus. The annealing station is arranged to anneal a wafer. The robot arm is arranged to transfer the wafer from the transfer chamber to the annealing station. The edge detector is disposed over the robot arm for the purpose of monitoring at least one portion of an edge bevel removal area of the wafer carried by the robot arm.Type: GrantFiled: May 15, 2015Date of Patent: May 12, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chao-Tung Wu, Kuo-Chung Yu, Chung-Hao Hu, Sheng-Ping Weng
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Publication number: 20160337621Abstract: A semiconductor apparatus includes a transfer chamber, an annealing station, a robot arm, and an edge detector. The transfer chamber is configured to interface with an electroplating apparatus. The annealing station is arranged to anneal a wafer. The robot arm is arranged to transfer the wafer from the transfer chamber to the annealing station. The edge detector is disposed over the robot arm for the purpose of monitoring at least one portion of an edge bevel removal area of the wafer carried by the robot arm.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: CHAO-TUNG WU, KUO-CHUNG YU, CHUNG-HAO HU, SHENG-PING WENG
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Publication number: 20050201391Abstract: A network address translation (NAT)-enabled device such as a router or gateway device includes a NAT facility for connecting at least two hosts inside a first network to a second network allowing the inside hosts to share an address of the second network, a gateway interface for connecting to a demilitarized zone (DMZ) host inside the first network, a disposer connected to the gateway interface for assigning an address of the second network to the DMZ host, and a dispatcher connected to the gateway interface and the NAT facility for communicating messages between the second network and the gateway interface or the NAT facility according to a medium access control (MAC) address of the message.Type: ApplicationFiled: March 11, 2004Publication date: September 15, 2005Inventors: Hung-Fang Ma, Pau-Chuan Ting, Kuo-Chung Yu, Lun-Jung Wang