Patents by Inventor Kuo-Cyuan Kuo
Kuo-Cyuan Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972113Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.Type: GrantFiled: July 26, 2022Date of Patent: April 30, 2024Assignee: Silicon Motion, Inc.Inventors: Bo-Chang Ye, Kuo-Cyuan Kuo, Chih-Chiang Chen
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Publication number: 20240036738Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.Type: ApplicationFiled: July 26, 2022Publication date: February 1, 2024Applicant: Silicon Motion, Inc.Inventors: Bo-Chang Ye, Kuo-Cyuan Kuo, Chih-Chiang Chen
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Publication number: 20230305711Abstract: A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.Type: ApplicationFiled: March 2, 2023Publication date: September 28, 2023Applicant: Silicon Motion, Inc.Inventors: Bo-Chang Ye, I-Ta Chen, Wen-Shu Chen, Kuo-Cyuan Kuo
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Patent number: 11636055Abstract: A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.Type: GrantFiled: September 15, 2021Date of Patent: April 25, 2023Assignee: Silicon Motion, Inc.Inventors: Wen-Shu Chen, Kuo-Cyuan Kuo, I-Ta Chen, Chih-Chiang Chen
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Publication number: 20230012997Abstract: A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.Type: ApplicationFiled: September 15, 2021Publication date: January 19, 2023Applicant: Silicon Motion, Inc.Inventors: Wen-Shu Chen, Kuo-Cyuan Kuo, I-Ta Chen, Chih-Chiang Chen
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Publication number: 20210278892Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.Type: ApplicationFiled: May 27, 2020Publication date: September 9, 2021Inventors: Kuo-Cyuan Kuo, Chih-Chiang Chen, I-Ta Chen
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Patent number: 11112855Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.Type: GrantFiled: May 27, 2020Date of Patent: September 7, 2021Assignee: Silicon Motion, Inc.Inventors: Kuo-Cyuan Kuo, Chih-Chiang Chen, I-Ta Chen
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Patent number: 10936046Abstract: A method for performing power saving control in memory device, the associated memory device and memory controller thereof, and the associated electronic device are provided, where the method is applicable to the memory controller, and the memory device includes the memory controller and a non-volatile (NV) memory. The method may include: during transmitting to a host device, sending end of burst (EOB)-related symbols to the host device, in order to notify the host device of EOB; controlling a physical layer (PHY) circuit to turn off a clock source within the PHY circuit, in order to save power, wherein the PHY circuit is positioned in a transmission interface circuit within the memory controller, and the transmission interface circuit is arranged to perform communications with the host device for the memory device; and when receiving a trigger signal from the host device, utilizing the PHY circuit to turn on the clock source.Type: GrantFiled: February 12, 2019Date of Patent: March 2, 2021Assignee: Silicon Motion, Inc.Inventors: Wen-Chi Chao, Kuo-Cyuan Kuo
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Publication number: 20190377402Abstract: A method for performing power saving control in memory device, the associated memory device and memory controller thereof, and the associated electronic device are provided, where the method is applicable to the memory controller, and the memory device includes the memory controller and a non-volatile (NV) memory. The method may include: during transmitting to a host device, sending end of burst (EOB)-related symbols to the host device, in order to notify the host device of EOB; controlling a physical layer (PHY) circuit to turn off a clock source within the PHY circuit, in order to save power, wherein the PHY circuit is positioned in a transmission interface circuit within the memory controller, and the transmission interface circuit is arranged to perform communications with the host device for the memory device; and when receiving a trigger signal from the host device, utilizing the PHY circuit to turn on the clock source.Type: ApplicationFiled: February 12, 2019Publication date: December 12, 2019Inventors: Wen-Chi Chao, Kuo-Cyuan Kuo
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Patent number: 8675799Abstract: A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.Type: GrantFiled: March 18, 2011Date of Patent: March 18, 2014Assignee: Etron Technology, Inc.Inventors: Huei-Chiang Shiu, Hsuan-Ching Chao, Kuo-Cyuan Kuo, Ming-Kia Chen
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Patent number: 8605777Abstract: A circuit for recognizing a beginning and a data rate of data includes at least two data rate detecting units and a post processing unit. The at least two data rate detecting units are used for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize a data rate of the data. The post processing unit is coupled to the at least two data rate detecting units for recognizing a beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized.Type: GrantFiled: March 17, 2011Date of Patent: December 10, 2013Assignee: Etron Technology, Inc.Inventors: Kuo-Cyuan Kuo, Cheng-Pin Huang, I-Ta Chen
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Patent number: 8588357Abstract: A phase selector capable of tolerating jitters is applied in a clock and data recovery circuit. The phase selector includes a comparing module, a weighting circuit, and a predictor. The comparing module compares a phase-detecting signal and a phase-selecting signal corresponding to the last cycle so as to generate an error signal. The weighting circuit calculates a weighting error signal according to the error signal and a weighting parameter. The phase predictor compares the weighting error signal and predetermined threshold values so as to generate the phase-selecting signal corresponding to the present cycle. When the received input data stream of the clock and data recovery circuit has a small jitter, the phase selector rapidly locks the phase so as to generate the correct phase-selecting signal. When the received input data stream of the clock and data recovery circuit has a large jitter, the phase selector stably generates the phase-selecting signal.Type: GrantFiled: October 27, 2011Date of Patent: November 19, 2013Assignee: Etron Technology, Inc.Inventors: Kuo-Cyuan Kuo, Huei-Chiang Shiu, Hsieh-Huan Yen
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Patent number: 8330535Abstract: An equalizer includes an oversampling logic unit, a direct current setting unit, and an alternating current setting unit. The oversampling logic unit oversamples data from a channel to generate a plurality of direct current terms and a plurality of alternating current terms according to an oversampling clock, and outputting a plurality of direct current terms corresponding to an output clock and a plurality of alternating current terms corresponding to the output clock according to the output clock. The direct current setting unit adjusts a direct current setting of the equalizer according to a plurality of direct current terms inputted by the oversampling logic unit within a first predetermined time. And the alternating current setting unit adjusts an alternating current setting of the equalizer according to a plurality of alternating current terms inputted by the oversampling logic unit within the first predetermined time.Type: GrantFiled: March 20, 2011Date of Patent: December 11, 2012Assignee: Etron Technology, Inc.Inventors: Kuo-Cyuan Kuo, Yu-Chiun Lin, Ming-Kia Chen
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Publication number: 20120121052Abstract: A phase selector capable of tolerating jitters is applied in a clock and data recovery circuit. The phase selector includes a comparing module, a weighting circuit, and a predictor. The comparing module compares a phase-detecting signal and a phase-selecting signal corresponding to the last cycle so as to generate an error signal. The weighting circuit calculates a weighting error signal according to the error signal and a weighting parameter. The phase predictor compares the weighting error signal and predetermined threshold values so as to generate the phase-selecting signal corresponding to the present cycle. When the received input data stream of the clock and data recovery circuit has a small jitter, the phase selector rapidly locks the phase so as to generate the correct phase-selecting signal. When the received input data stream of the clock and data recovery circuit has a large jitter, the phase selector stably generates the phase-selecting signal.Type: ApplicationFiled: October 27, 2011Publication date: May 17, 2012Inventors: Kuo-Cyuan Kuo, Huei-Chiang Shiu, Hsieh-Huan Yen
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Publication number: 20110292986Abstract: A circuit for recognizing a beginning and a data rate of data includes at least two data rate detecting units and a post processing unit . The at least two data rate detecting units are used for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize a data rate of the data. The post processing unit is coupled to the at least two data rate detecting units for recognizing a beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized.Type: ApplicationFiled: March 17, 2011Publication date: December 1, 2011Inventors: Kuo-Cyuan Kuo, Cheng-Pin Huang, I-Ta Chen
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Publication number: 20110293055Abstract: A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.Type: ApplicationFiled: March 18, 2011Publication date: December 1, 2011Inventors: Huei-Chiang Shiu, Hsuan-Ching Chao, Kuo-Cyuan Kuo, Ming-Kia Chen
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Publication number: 20110291774Abstract: An equalizer includes an oversampling logic unit, a direct current setting unit, and an alternating current setting unit. The oversampling logic unit oversamples data from a channel to generate a plurality of direct current terms and a plurality of alternating current terms according to an oversampling clock, and outputting a plurality of direct current terms corresponding to an output clock and a plurality of alternating current terms corresponding to the output clock according to the output clock. The direct current setting unit adjusts a direct current setting of the equalizer according to a plurality of direct current terms inputted by the oversampling logic unit within a first predetermined time. And the alternating current setting unit adjusts an alternating current setting of the equalizer according to a plurality of alternating current terms inputted by the oversampling logic unit within the first predetermined time.Type: ApplicationFiled: March 20, 2011Publication date: December 1, 2011Inventors: Kuo-Cyuan Kuo, Yu-Chiun Lin, Ming-Kia Chen