Patents by Inventor Kuo-Fang Huang
Kuo-Fang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11367727Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.Type: GrantFiled: October 21, 2020Date of Patent: June 21, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Patent number: 11367728Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.Type: GrantFiled: October 21, 2020Date of Patent: June 21, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Publication number: 20210043633Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.Type: ApplicationFiled: October 21, 2020Publication date: February 11, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Publication number: 20210035980Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.Type: ApplicationFiled: October 21, 2020Publication date: February 4, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Patent number: 10868017Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively.Type: GrantFiled: March 19, 2019Date of Patent: December 15, 2020Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Patent number: 10861858Abstract: A static random-access memory structure includes a substrate, a first conductive type transistor, a second conductive type transistor and a capacitor unit. The first conductive type transistor and the second conductive type transistor are disposed on the surface of the substrate, and the capacitor unit is positioned between the transistors. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode includes a plurality of first protrudent portions and a planar portion. The first protrudent portions are connected to the first planar portion and protrude from the top surface of the planar portion. The second electrode covers the top surface of the first protrudent portions and formed between adjacent first protrudent portions.Type: GrantFiled: April 25, 2019Date of Patent: December 8, 2020Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Yu-Cheng Lu, Kuo-Fang Huang, Chia-Hsien Kuo
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Publication number: 20200235102Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.Type: ApplicationFiled: March 19, 2019Publication date: July 23, 2020Applicant: Powerchip Technology CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
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Publication number: 20200219891Abstract: A static random-access memory structure includes a substrate, a first conductive type transistor, a second conductive type transistor and a capacitor unit. The first conductive type transistor and the second conductive type transistor are disposed on the surface of the substrate, and the capacitor unit is positioned between the transistors. The capacitor unit includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode includes a plurality of first protrudent portions and a planar portion. The first protrudent portions are connected to the first planar portion and protrude from the top surface of the planar portion. The second electrode covers the top surface of the first protrudent portions and formed between adjacent first protrudent portions.Type: ApplicationFiled: April 25, 2019Publication date: July 9, 2020Inventors: Shih-Ping Lee, Yu-Cheng Lu, Kuo-Fang Huang, Chia-Hsien Kuo
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Patent number: 9825547Abstract: A multi-level DC-DC converter device includes an inverter, a 3-winding high-frequency transformer, a first full-bridge rectifier, a second full-bridge rectifier, a selective circuit and a filter circuit. A first winding at a primary side of the high-frequency transformer connects with the inverter while a second winding and a third winding of at a secondary side of the high-frequency transformer connect with the first full-bridge rectifier and the second full-bridge rectifier. The selective circuit connects with DC output ports of the first full-bridge rectifier and the second full-bridge rectifier, thereby operationally selecting two serially-connected full-bridge rectifiers or single full-bridge rectifier to output two voltage levels performed as a multi-level output voltage. The filter circuit connects between the selective circuit and a load for filtering harmonics and outputting a DC voltage.Type: GrantFiled: July 6, 2016Date of Patent: November 21, 2017Assignee: Ablerex Electronics Co., Ltd.Inventors: Wen-Jung Chiang, Kuo-Fang Huang, Wen-Chung Chen
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Patent number: 9787201Abstract: A DC-DC converter is operated in a boost mode by operating a plurality of low-voltage side switches with a first fixed duty cycle (greater than 0.5), with cutting off a plurality of the first high-voltage side switches and a plurality of the second high-voltage side switches, with conducting a plurality of the first diodes of the first high-voltage side switches and a plurality of the second diodes of the second high-voltage side switches, and with alternatively conducting and cutting off a bidirectional switch. In a buck mode, the low-voltage side switches are cut off and a plurality of diodes of the low-voltage side switches are conducted. Furthermore, the first high-voltage side switches are complemented and are operated with a second fixed duty cycle (less than 0.5) while the second high-voltage side switches are conducted and cut off alternatively and the bidirectional switch is switched on and off.Type: GrantFiled: July 6, 2016Date of Patent: October 10, 2017Assignee: Ablerex Electronics Co., Ltd.Inventors: Wen-Jung Chiang, Kuo-Fang Huang, Wen-Chung Chen
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Publication number: 20170264205Abstract: A DC-DC converter is operated in a boost mode by operating a plurality of low-voltage side switches with a first fixed duty cycle (greater than 0.5), with cutting off a plurality of the first high-voltage side switches and a plurality of the second high-voltage side switches, with conducting a plurality of the first diodes of the first high-voltage side switches and a plurality of the second diodes of the second high-voltage side switches, and with alternatively conducting and cutting off a bidirectional switch. In a buck mode, the low-voltage side switches are cut off and a plurality of diodes of the low-voltage side switches are conducted. Furthermore, the first high-voltage side switches are complemented and are operated with a second fixed duty cycle (less than 0.5) while the second high-voltage side switches are conducted and cut off alternatively and the bidirectional switch is switched on and off.Type: ApplicationFiled: July 6, 2016Publication date: September 14, 2017Inventors: Wen-Jung Chiang, Kuo-Fang Huang, Wen-Chung Chen
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Publication number: 20170207712Abstract: A multi-level DC-DC converter device includes an inverter, a 3-winding high-frequency transformer, a first full-bridge rectifier, a second full-bridge rectifier, a selective circuit and a filter circuit. A first winding at a primary side of the high-frequency transformer connects with the inverter while a second winding and a third winding of at a secondary side of the high-frequency transformer connect with the first full-bridge rectifier and the second full-bridge rectifier. The selective circuit connects with DC output ports of the first full-bridge rectifier and the second full-bridge rectifier, thereby operationally selecting two serially-connected full-bridge rectifiers or single full-bridge rectifier to output two voltage levels performed as a multi-level output voltage. The filter circuit connects between the selective circuit and a load for filtering harmonics and outputting a DC voltage.Type: ApplicationFiled: July 6, 2016Publication date: July 20, 2017Inventors: Wen-Jung Chiang, Kuo-Fang Huang, Wen-Chung Chen
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Publication number: 20090235894Abstract: A lubrication apparatus for an engine includes a crankshaft chamber, a camshaft chamber, and an oil reservoir chamber, wherein an oil-suction piping path is provided in the oil reservoir chamber, and is communicated between the crankshaft chamber and the oil reservoir chamber. The oil-suction piping path includes, among others, a rotatable pipe including a plurality of oil-suction orifices located at wall of the rotatable pipe. No matter the engine is situated at any state of declination, at least one of the oil-suction orifices and an air-suction vent is kept under the surface of the lubricant, so that the engine can be appropriately lubricated. Further, a one-way valve is arranged between the crankshaft chamber and the oil reservoir chamber, where most of the lubricant can flow back to the oil reservoir chamber during the descending stroke of a piston, so that a lubricant supply can be reduced.Type: ApplicationFiled: March 20, 2009Publication date: September 24, 2009Applicant: Sanyang Industry Co. Ltd.Inventors: Jia-Ling Lee, Shin-Chang Lee, Chen-Tung Lai, Kuo-Fang Huang
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Patent number: 7345380Abstract: A backup power supply system supplies power from a first ac power source in normal condition. Once the first ac power source is abnormal or fails, the system automatically turns off the first ac power source and turns on a second ac power source with null transfer time. When the first ac power source is normal, a dc/ac power inverter is controlled to supply an approximately null current such that a mechanical switch is allowed to be closed and no circulating current is generated between the first ac power source and the dc/ac power inverter. Since the mechanical switch is continuously closed, and requires no switching operation, the backup power supply system can supply the backup power with a null transfer time.Type: GrantFiled: June 29, 2004Date of Patent: March 18, 2008Assignee: UIS Abler Electronics Co., Ltd.Inventors: Ya-Tsung Feng, Chin-Chang Wu, Hung-Liang Chou, Nan-Ying Shen, Kuo-Fang Huang, Yao-Jen Chang
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Publication number: 20050088043Abstract: A backup power supply system supplies power from a first ac power source in normal condition. Once the first ac power source is abnormal or failed, the system automatically turns off the first ac power source and turns on a second ac power source with null transfer time. When the first ac power source is normal, a dc/ac power inverter is controlled to supply an approximately null current that a mechanical switch is allowed to being closed and no circulating current is generated between the first ac power source and the dc/ac power inverter. Since the mechanical switch is successively closed, and it requires no switching operation, the backup power supply system can supply the backup power with a null transfer time.Type: ApplicationFiled: June 29, 2004Publication date: April 28, 2005Applicant: UIS Abler Electronics Co., Ltd.Inventors: Ya-Tsung Feng, Chin-Chang Wu, Hung-Liang Chou, Nan-Ying Shen, Kuo-Fang Huang, Yao-Jen Chang