Patents by Inventor Kuo-Feng Yu
Kuo-Feng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12218213Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.Type: GrantFiled: February 22, 2022Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: An-Hung Tai, Jian-Hao Chen, Hui-Chi Chen, Kuo-Feng Yu
-
Publication number: 20250040218Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.Type: ApplicationFiled: July 26, 2024Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung TSAI, Clement Hsingjen WANN, Kuo-Feng YU, Ming-Hsi YEH, Shahaji B. MORE, Yu-Ming LIN
-
Patent number: 12170327Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.Type: GrantFiled: August 10, 2021Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Te Chen, Hui-Ting Tsai, Jun He, Kuo-Feng Yu, Chun Hsiung Tsai
-
Patent number: 12171091Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.Type: GrantFiled: August 9, 2023Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
-
Publication number: 20240413221Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: ApplicationFiled: July 11, 2024Publication date: December 12, 2024Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
-
Patent number: 12154964Abstract: A semiconductor device includes an interface layer on a substrate, a gate dielectric layer on the interface layer, and a work function metal layer on the gate dielectric layer. An interface between the interface layer and the gate dielectric layer has a concentration of a dipole-inducing element. The semiconductor device also includes an oxygen blocking layer on the work function metal layer and a metal fill layer on the oxygen blocking layer.Type: GrantFiled: November 22, 2021Date of Patent: November 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: An-Hung Tai, Yung-Hsiang Chan, Shan-Mei Liao, Hsin-Han Tsai, Jian-Hao Chen, Kuo-Feng Yu
-
Publication number: 20240387277Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.Type: ApplicationFiled: July 25, 2024Publication date: November 21, 2024Inventors: Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Shan-Mei Liao, Jer-Fu Wang, Yung-Hsiang Chan
-
Publication number: 20240387682Abstract: A method of forming a semiconductor device includes removing a dummy gate structure to expose a channel region, depositing an interface layer on the channel region, depositing a gate dielectric layer on the interface layer, and forming a doping layer on the gate dielectric layer. The doping layer includes a dipole-inducing element. The method also includes annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer, removing the doping layer, forming a work function metal layer on the gate dielectric layer, depositing an oxygen blocking layer on the work function metal layer, and forming a gate metal fill layer on the oxygen blocking layer.Type: ApplicationFiled: July 25, 2024Publication date: November 21, 2024Inventors: An-Hung Tai, Yung-Hsiang Chan, Shan-Mei Liao, Hsin-Han Tsai, Jian-Hao Chen, Kuo-Feng Yu
-
Publication number: 20240387670Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Kuo-Feng Yu, Jiao-Hao Chen, Chih-Yu Hsu, Chih-Wei Lee, Chien-Yuan Chen
-
Publication number: 20240387639Abstract: A semiconductor structure includes a stack of nanostructures, an interfacial layer wrapping around each nanostructure of the stack of nanostructures, a first gate dielectric layer wrapping around the interfacial layer and each nanostructure of the stack of nanostructures, and a gate electrode layer disposed over the first gate dielectric layer. The first gate dielectric layer includes a dipole element. A first concentration of the dipole element at a center line of the first gate dielectric layer is greater than a second concentration of the dipole element at a boundary surface of the first gate dielectric layer interfacing the interfacial layer.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Shan-Mei Liao, Yung-Hsiang Chan, Yao-Teng Chuang, Jian-Hao Chen, Kuo-Feng Yu
-
Publication number: 20240379365Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Kuo-Feng Yu, Chun Hsiung Tsai, Jian-Hao Chen, Hoong Shing Wong, Chih-Yu Hsu
-
Publication number: 20240381608Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
-
Publication number: 20240379364Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
-
Publication number: 20240379825Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
-
Publication number: 20240379814Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
-
Publication number: 20240379796Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
-
Patent number: 12142640Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.Type: GrantFiled: September 22, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shan-Mei Liao, Yung-Hsiang Chan, Yao-Teng Chuang, Jian-Hao Chen, Kuo-Feng Yu
-
Patent number: 12142657Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.Type: GrantFiled: April 13, 2022Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Feng Yu, Jiao-Hao Chen, Chih-Yu Hsu, Chih-Wei Lee, Chien-Yuan Chen
-
Patent number: 12142663Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.Type: GrantFiled: July 24, 2023Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
-
Publication number: 20240371974Abstract: A method of manufacturing a semiconductor device includes: depositing a first dielectric layer and a second dielectric layer over a substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; removing the dummy gate electrode and forming a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate; and performing a first treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the substrate, the LDD regions and the ILD layer.Type: ApplicationFiled: July 22, 2024Publication date: November 7, 2024Inventors: CHUN HSIUNG TSAI, KUO-FENG YU, YU-MING LIN, CLEMENT HSINGJEN WANN