Patents by Inventor Kuo-Fu Chen

Kuo-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240120735
    Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Chia-Lin HSU, Ming-Fu TSAI, Yu-Ti SU, Kuo-Ji CHEN
  • Publication number: 20240112963
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area, a first die area and a second die area. The first die area and the second die area are separated by the scribe line area extending along a first direction. The test structure is disposed in the scribe line area. The test structure includes a test device and a first test pad. The test device has a physical characteristic similar to a semiconductor device fabricated in the first die area or the second die area. The first test pad is electrically connected to the test device. A first distance between the first test pad and the first die area gradually increases from a center region to a peripheral region of the first test pad in the first direction.
    Type: Application
    Filed: August 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Tung CHEN, Pei-Haw TSAO, Kuo-Lung FAN, Yuan-Fu CHUNG
  • Publication number: 20240110576
    Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Inventors: Wei-I LING, Chao-Fu YANG, Chih-Chung CHEN, Kuo-Tung HSU
  • Patent number: 11928416
    Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
  • Patent number: 5605054
    Abstract: An apparatus for reclaiming refrigerant including a distillation tank, an eliminator arranged within an upper portion of said distillation tank, a booster connected to an upper end of the distillation tank for extracting refrigerant vapor from the distillation tank, a heat exchanger connected to the booster, a heat pump for transferring condensing heat from the heat exchanger to the distillation tank, and an air/water/refrigerant separator connected to the heat exchanger, whereby the apparatus can effectively reclaim refrigerant and separate air and water from the refrigerant.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: February 25, 1997
    Assignee: Chief Havc Engineering Co., Ltd.
    Inventor: Kuo-Fu Chen