Abstract: A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.

Abstract: An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor.

Abstract: An integrated circuit for controlling a slave device is provided. The integrated circuit includes a pin, a micro-controller and an inter integrated circuit (I2C) bus controller coupled between the micro-controller and the pin. The I2C bus controller includes a transceiver unit coupled to the slave device via the pin, and an interface unit coupled between the transceiver unit and the micro-controller. The interface unit includes a start control register and a stop control register. The start control register provides a start signal to the slave device via the transceiver unit when the start control register is programmed by the micro-controller. The stop control register provides a stop signal to the slave device via the transceiver unit when the stop control register is programmed by the micro-controller. The micro-controller programs the stop control register according to an interrupt signal from the interface unit.

Abstract: A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off.

Abstract: An integrated circuit for controlling a slave device is provided. The integrated circuit includes a pin, a micro-controller and an inter integrated circuit (I2C) bus controller coupled between the micro-controller and the pin. The I2C bus controller includes a transceiver unit coupled to the slave device via the pin, and an interface unit coupled between the transceiver unit and the micro-controller. The interface unit includes a start control register and a stop control register. The start control register provides a start signal to the slave device via the transceiver unit when the start control register is programmed by the micro-controller. The stop control register provides a stop signal to the slave device via the transceiver unit when the stop control register is programmed by the micro-controller. The micro-controller programs the stop control register according to an interrupt signal from the interface unit.

Abstract: An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.

Abstract: An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor.

Abstract: A computer system for processing data in a non-operational state and processing method thereof are provided. The computer system includes a data output unit, a data source, a data processing module and a state monitor unit. The data processing module accesses and processes data from the data source, and transmits the processed data to the data output unit. The state monitor unit monitors a power supply state of the computer system to generate a state switch signal, which indicates whether the computer system is in an operational state or a non-operational state. When the state switch signal indicates that the computer system is in a non-operational state, the data source and the data processing module receives operating voltages to access and process data.

Abstract: A computer system and a power-management method thereof are provided. The computer system has an image-reading mode, a first power-management mode and a second power-management mode, and the computer system operating in the second power-management mode consumes less power than it consumes in the first power-management mode. The computer system comprises a first portion comprising a graphics processing unit, a memory space and a display; and a second portion comprising a storage storing an image data. When the computer system operates in the image-reading mode, the image data has been transferred to the memory space from the storage, the second portion enters to the second power-management mode from the first power-management mode, and the first portion keeps in the first power-management mode, so that the graphics processing unit can display an image by the display according to the image data stored in the memory space.

Abstract: A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off.

Abstract: An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.

Abstract: A computer system and a power-management method thereof are provided. The computer system has an image-reading mode, a first power-management mode and a second power-management mode, and the computer system operating in the second power-management mode consumes less power than it consumes in the first power-management mode. The computer system comprises a first portion comprising a graphics processing unit, a memory space and a display; and a second portion comprising a storage storing an image data. When the computer system operates in the image-reading mode, the image data has been transferred to the memory space from the storage, the second portion enters to the second power-management mode from the first power-management mode, and the first portion keeps in the first power-management mode, so that the graphics processing unit can display an image by the display according to the image data stored in the memory space.

Abstract: A device information management system for managing device information of various peripheral devices is disclosed. The system includes a central processing unit, a logic controller connected with the central processing unit, a first device connected with the logic controller, wherein the first device has a device information stored in a memory unit for identifying the first device, and a second device connected with the first device, wherein the first device outputs an access command to the second device and the second device accesses the memory unit to retrieve the device information of the first device according to the access command.

Abstract: A computer system for processing data in a non-operational state and processing method thereof are provided. The computer system includes a data output unit, a data source, a data processing module and a state monitor unit. The data processing module accesses and processes data from the data source, and transmits the processed data to the data output unit. The state monitor unit monitors a power supply state of the computer system to generate a state switch signal, which indicates whether the computer system is in an operational state or a non-operational state. When the state switch signal indicates that the computer system is in a non-operational state, the data source and the data processing module receives operating voltages to access and process data.