Abstract: The present invention provides a control method of a flash memory controller, which includes the steps of: setting a waiting time in an interrupt coalescing mechanism, and setting a timer, wherein a timeout value of the timer is equal to the waiting time; receiving multiple commands from a submission queue in a host device, generating multiple command responses after processing the multiple commands, and writing the multiple command responses to a completion queue in the host device; receiving a submission queue tail and a completion queue head from the host device; and when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain a queue depth of a command queue of the host device.

Abstract: The present invention provides a control method of a flash memory controller, which includes the steps of: setting a waiting time in an interrupt coalescing mechanism, and setting a timer, wherein a timeout value of the timer is equal to the waiting time; receiving multiple commands from a submission queue in a host device, generating multiple command responses after processing the multiple commands, and writing the multiple command responses to a completion queue in the host device; receiving a submission queue tail and a completion queue head from the host device; and when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain a queue depth of a command queue of the host device.