Abstract: A new method is provided for the creation of PIP capacitors for mixed-mode processes. The process starts with the creation of Shallow Trench Isolation regions in the surface of a substrate, defining active regions and the region over which the PIP capacitor is to be created on the surface of the substrate. The PIP STI region is etched, lowering the surface of the PIP STI region. A first layer of polysilicon is selectively deposited in the opening created in the layer of STI over which the PIP is to be created, the first layer of polysilicon is polished. The wells for the isolation of the gate electrode and the PIP STI region are implanted in the surface of the substrate. A layer of insulation, serving as the layer of dielectric for the capacitor, is blanket deposited over the surface of the substrate. The deposited layer of insulation is patterned and etched, leaving the layer of insulation in place overlying the first layer of polysilicon.

Abstract: A new method is provided for the creation of PIP capacitors for mixed-mode processes. The process starts with the creation of Shallow Trench Isolation regions in the surface of a substrate, defining active regions and the region over which the PIP capacitor is to be created on the surface of the substrate. The PIP STI region is etched, lowering the surface of the PIP STI region. A first layer of polysilicon is selectively deposited in the opening created in the layer of STI over which the PIP is to be created, the first layer of polysilicon is polished. The wells for the isolation of the gate electrode and the PIP STI region are implanted in the surface of the substrate. A layer of insulation, serving as the layer of dielectric for the capacitor, is blanket deposited over the surface of the substrate. The deposited layer of insulation is patterned and etched, leaving the layer of insulation in place overlying the first layer of polysilicon.

Abstract: A new method is provided for the creation of PIP capacitors for mixed-mode processes. The process starts with the creation of Shallow Trench Isolation regions in the surface of a substrate, defining active regions and the region over which the PIP capacitor is to be created on the surface of the substrate. The PIP STI region is etched, lowering the surface of the PIP STI region. A first layer of polysilicon is selectively deposited in the opening created in the layer of STI over which the PIP is to be created, the first layer of polysilicon is polished. The wells for the isolation of the gate electrode and the PIP STI region are implanted in the surface of the substrate. A layer of insulation, serving as the layer of dielectric for the capacitor, is blanket deposited over the surface of the substrate. The deposited layer of insulation is patterned and etched, leaving the layer of insulation in place overlying the first layer of polysilicon.

Abstract: The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

Abstract: The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.