Patents by Inventor Kuo-Hsi LEE

Kuo-Hsi LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure with resist protective oxide on isolation structure and method of manufacturing the same
    Patent number: 10083860
    Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chia-Yao Liang, Jui-Long Chen, Sheng-Yuan Lin, Yi-Lii Huang, Kuo-Hsi Lee, Po-An Chen
  • SEMICONDUCTOR STRUCTURE WITH RESIST PROTECTIVE OXIDE ON ISOLATION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170229343
    Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang LIAO, Chia-Yao LIANG, Jui-Long CHEN, Sheng-Yuan LIN, Yi-Lii HUANG, Kuo-Hsi LEE, Po-An CHEN
  • Semiconductor structure with resist protective oxide on isolation structure and method of manufacturing the same
    Patent number: 9633860
    Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chia-Yao Liang, Jui-Long Chen, Sheng-Yuan Lin, Yi-Lii Huang, Kuo-Hsi Lee, Po-An Chen
  • SEMICONDUCTOR STRUCTURE WITH RESIST PROTECTIVE OXIDE ON ISOLATION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170011925
    Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 12, 2017
    Inventors: Chen-Liang LIAO, Chia-Yao LIANG, Jui-Long CHEN, Sheng-Yuan LIN, Yi-Lii HUANG, Kuo-Hsi LEE, Po-An CHEN