Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected.

Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.

Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.

Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

Abstract: An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of first through fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The SRAM cell further includes first through sixth gates configured to engage the channel regions of the first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected. The SRAM cell further includes first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate. The SRAM cell further includes second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose the first source/drain region. At least part of the spacer material is removed to expose the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure are formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose the first source/drain region. At least part of the spacer material is removed to expose the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.