Abstract: A method according to the present disclosure includes receiving a structure. The structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. The method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

Abstract: A semiconductor structure includes a first transistor and a second transistor, and a dielectric structure separating the first transistor from the second transistor. The first transistor includes a first gate structure and the second transistor includes a second gate structure. The dielectric structure includes a first portion sandwiched between the first gate structure and the second gate structure along a first direction, and a second portion protruding from the first portion along a second direction perpendicular to the first direction. The first portion has a first width and the second portion has a second width less than the first width, the first width and the second width being along the first direction, and the first portion has a first height and the second portion has a second height less than the first height.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: A semiconductor structure includes a substrate, a fin-shaped structure protruding from the substrate and orienting lengthwise along a first direction, an isolation feature disposed over the substrate and along a sidewall of a bottom portion of the fin-shaped structure, and a metal gate structure disposed over the fin-shaped structure and the isolation feature and orienting lengthwise along a second direction perpendicular to the first direction. The metal gate structure includes a bottom portion sandwiched between the isolation feature and the bottom portion of the fin-shaped structure along the second direction.

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.

Abstract: A memory cell includes first through fifth gate structures that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.

Abstract: A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.

Abstract: A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. one of the cells which is coupled to one of the first input pads and one of the second input pads is turned on, and a current flowing through the turned-on cell is measured.

Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.

Abstract: A semiconductor device includes a first transistor and a well strap feature disposed over a doped region of a first type dopant. The first transistor includes a first gate structure engaging a first channel region and a first epitaxial feature abutting the first channel region. The well-strap feature incudes a plurality of first nanostructures vertically stacked, a second gate structure wrapping around each of the first nanostructures, and a second epitaxial feature abutting the first nanostructures. The well-strap feature is configured to bias the doped region by electrically connecting the second epitaxial feature to a bias voltage.

Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.

Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.