Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.

Abstract: A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.

Abstract: A method for forming metal bumps is disclosed, comprising: providing a substrate including a plurality of pads; forming a solder mask on the substrate, wherein the solder mask has first openings to expose the pads; forming a photoresist layer on the solder mask, wherein the photoresist layer has second openings to expose the pads; forming a conductive layer on the phototresist layer, wherein a sidewall of each second opening, a sidewall of each first opening and the pads are covered with the conductive layer; forming a metal layer on the conductive layer by electroplating to fill the first and second openings; performing a planarization step to remove the conductive layer and the metal layer on the photoresist layer so as to remain the conductive layer and the metal layer in the first and second openings; removing the photoresist layer and performing a reflow step to form metal bumps.

Abstract: A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.

Abstract: A heat dissipation module suitable for performing heat dissipation on a heat source is provided. The heat dissipation module includes a first base, a first radiator, a thermoelectric cooler and a second radiator. The first base has a first surface and a second surface, wherein the first surface contacts the heat source. Both the first radiator and the thermoelectric cooler contact the second surface, while the second radiator is disposed on the thermoelectric cooler.

Abstract: A multi-mode operation system and method for computer systems is proposed. The system includes a storage device having first and second disk partitions, a mode controller and a master boot program. The master boot program checks the status of the mode controller. If the computer system is running in PC mode, the master boot program hides the second disk partition, boots from the first disk partition, and loads a complete version of an operating system therein, thereby enables the computer system to run in the PC mode. If the computer system is running in a sub-mode being defined as an entry of a multimedia mode class, such as a music playing mode or video playing mode, the master boot program activates the second disk partition, boots therefrom, and loads a refined version of the operating system therein, thereby enables the computer system to run in the selected sub-mode.

Abstract: Anti-shock mechanisms for electronic devices are provided. An anti-shock mechanism includes a plurality of first rods and first buffers. The first rods perpendicularly project from a first side of the electronic device, wherein the first side is substantially parallel to a moving direction of the vehicle. Each of the first buffers comprises a first opening, and the first rods are inserted in the first openings respectively.

Abstract: A multi-mode operation system and method for computer systems is proposed. The system includes a storage device having first and second disk partitions, a mode controller and a master boot program. The master boot program checks the status of the mode controller. If the computer system is running in PC mode, the master boot program hides the second disk partition, boots from the first disk partition, and loads a complete version of an operating system therein, thereby enables the computer system to run in the PC mode. If the computer system is running in a sub-mode being defined as an entry of a multimedia mode class, such as a music playing mode or video playing mode, the master boot program activates the second disk partition, boots therefrom, and loads a refined version of the operating system therein, thereby enables the computer system to run in the selected sub-mode.

Abstract: A method to improve nitride floating gate charge trapping for NROM flash memory device is disclosed. The present invention uses the SiON to replace the SiN of the NROM floating gate of the prior art. This arrangement improves the endurance and the reliability of the device and also extends data retention times. The present invention also discloses the integrated processes to fabricate the NROM flash memory device. Using the processes, the steps of fabricating the NROM are efficiently reduced, and the defects caused by the cleaning steps are eliminated.