Patents by Inventor Kuo-Hua Chang
Kuo-Hua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250176314Abstract: A method for manufacturing a light-emitting device includes steps of providing a substrate, the substrate having a first surface and a second surface that are opposite to each other; forming a nucleation layer on the first surface of the substrate by deposition, the nucleation layer having an upper surface that is uneven; forming a plurality of first voids, the plurality of first voids extending in a direction from the nucleation layer to the substrate, each of the plurality of first voids having an aspect ratio that is greater than 1, and a diameter that is no greater than 300 nm; forming an AlxGa1-xN layer on the nucleation layer to form an even surface, x>0.5; and forming a semiconductor epitaxial structure on the AlxGa1-xN layer. A light-emitting device manufactured by the above method is also provided.Type: ApplicationFiled: January 17, 2025Publication date: May 29, 2025Inventors: MISAICHI TAKEUCHI, Zhongjie YANG, KUO-HUA CHANG, YUNGLING LAN, JING-FENG HUANG
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Patent number: 7550375Abstract: A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.Type: GrantFiled: December 8, 2006Date of Patent: June 23, 2009Assignee: Advanced Semiconductor Engineering Inc.Inventors: Sheng-Ming Wang, Shuo-Hsun Chang, Kuo-Hua Chang, Chi-Chih Huang, Chih-Cheng Chen
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Publication number: 20070232051Abstract: A method for forming metal bumps is disclosed, comprising: providing a substrate including a plurality of pads; forming a solder mask on the substrate, wherein the solder mask has first openings to expose the pads; forming a photoresist layer on the solder mask, wherein the photoresist layer has second openings to expose the pads; forming a conductive layer on the phototresist layer, wherein a sidewall of each second opening, a sidewall of each first opening and the pads are covered with the conductive layer; forming a metal layer on the conductive layer by electroplating to fill the first and second openings; performing a planarization step to remove the conductive layer and the metal layer on the photoresist layer so as to remain the conductive layer and the metal layer in the first and second openings; removing the photoresist layer and performing a reflow step to form metal bumps.Type: ApplicationFiled: October 31, 2006Publication date: October 4, 2007Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Sheng-Ming Wang, Shuo-Hsun Chang, Kuo-Hua Chang, Chi-Chih Huang, Chih-Cheng Chen
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Publication number: 20070218676Abstract: A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.Type: ApplicationFiled: December 8, 2006Publication date: September 20, 2007Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Sheng-Ming Wang, Shuo-Hsun Chang, Kuo-Hua Chang, Chi-Chih Huang, Chih-Cheng Chen
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Publication number: 20070163269Abstract: A heat dissipation module suitable for performing heat dissipation on a heat source is provided. The heat dissipation module includes a first base, a first radiator, a thermoelectric cooler and a second radiator. The first base has a first surface and a second surface, wherein the first surface contacts the heat source. Both the first radiator and the thermoelectric cooler contact the second surface, while the second radiator is disposed on the thermoelectric cooler.Type: ApplicationFiled: November 30, 2006Publication date: July 19, 2007Applicant: ASUSTeK COMPUTER INC.Inventors: Chao-Tsai Chung, Kuo-Hua Chang
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Patent number: 7228408Abstract: A multi-mode operation system and method for computer systems is proposed. The system includes a storage device having first and second disk partitions, a mode controller and a master boot program. The master boot program checks the status of the mode controller. If the computer system is running in PC mode, the master boot program hides the second disk partition, boots from the first disk partition, and loads a complete version of an operating system therein, thereby enables the computer system to run in the PC mode. If the computer system is running in a sub-mode being defined as an entry of a multimedia mode class, such as a music playing mode or video playing mode, the master boot program activates the second disk partition, boots therefrom, and loads a refined version of the operating system therein, thereby enables the computer system to run in the selected sub-mode.Type: GrantFiled: March 9, 2004Date of Patent: June 5, 2007Assignee: Acer Inc.Inventors: Chien-Hao Wu, Kuo-Hua Chang, Ming-Chih Ko, Shih-Chieh Kuo
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Publication number: 20060261620Abstract: Anti-shock mechanisms for electronic devices are provided. An anti-shock mechanism includes a plurality of first rods and first buffers. The first rods perpendicularly project from a first side of the electronic device, wherein the first side is substantially parallel to a moving direction of the vehicle. Each of the first buffers comprises a first opening, and the first rods are inserted in the first openings respectively.Type: ApplicationFiled: May 3, 2006Publication date: November 23, 2006Applicant: BENQ CORPORATIONInventors: Lung-Chi Lu, Kuo-Hua Chang
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Publication number: 20040205396Abstract: A multi-mode operation system and method for computer systems is proposed. The system includes a storage device having first and second disk partitions, a mode controller and a master boot program. The master boot program checks the status of the mode controller. If the computer system is running in PC mode, the master boot program hides the second disk partition, boots from the first disk partition, and loads a complete version of an operating system therein, thereby enables the computer system to run in the PC mode. If the computer system is running in a sub-mode being defined as an entry of a multimedia mode class, such as a music playing mode or video playing mode, the master boot program activates the second disk partition, boots therefrom, and loads a refined version of the operating system therein, thereby enables the computer system to run in the selected sub-mode.Type: ApplicationFiled: March 9, 2004Publication date: October 14, 2004Inventors: Chien-Hao Wu, Kuo-Hua Chang, Ming-Chih Ko, Shih-Chieh Kuo
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Patent number: 6444521Abstract: A method to improve nitride floating gate charge trapping for NROM flash memory device is disclosed. The present invention uses the SiON to replace the SiN of the NROM floating gate of the prior art. This arrangement improves the endurance and the reliability of the device and also extends data retention times. The present invention also discloses the integrated processes to fabricate the NROM flash memory device. Using the processes, the steps of fabricating the NROM are efficiently reduced, and the defects caused by the cleaning steps are eliminated.Type: GrantFiled: November 9, 2000Date of Patent: September 3, 2002Assignee: Macronix International Co., Ltd.Inventors: Kent Kuo-Hua Chang, Cheng-Chen Calvin Hsueh