Patents by Inventor Kuo-Hua LIU

Kuo-Hua LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9136241
    Abstract: An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 15, 2015
    Inventors: Yu-Lin Yen, Kuo-Hua Liu, Yu-Lung Huang, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 8993365
    Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 31, 2015
    Assignee: Xintec Inc.
    Inventors: Yi-Ming Chang, Kuo-Hua Liu, Yi-Cheng Wang, Sheng-Yen Chang
  • Publication number: 20140242742
    Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: XINTEC INC.
    Inventors: Yi-Ming CHANG, Kuo-Hua LIU, Yi-Cheng WANG, Sheng-Yen CHANG
  • Patent number: 8748926
    Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 ?m; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 10, 2014
    Inventors: Kuo-Hua Liu, Yi-Ming Chang, Hsi-Chien Lin
  • Publication number: 20120261809
    Abstract: An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 18, 2012
    Inventors: Yu-Lin YEN, Kuo-Hua LIU, Yu-Lung HUANG, Tsang-Yu LIU, Yen-Shih HO