Abstract: A system and a method for processing storage device occurring abnormal power interruption are provided. The method includes the following steps: (a) providing data to the storage device by a master controller; (b) outputting an address storing instruction from the master controller; (c) storing an address of a storage block in an address storage; (d) executing a program for accessing the data by the storage device; (e) determining whether the storage device is abnormally powered down by the master controller, if yes, performing step (f), and if not, performing step (g) after completing the execution of the program; (f) instructing an storage control circuit of the storage device to execute an error processing procedure on the storage block corresponding to the address by the master controller, and then performing step (a); (g) clearing the address stored in the address storage according to an instruction from the master controller.

Abstract: A method for accessing data by a solid state disk is provided, which includes steps of: configuring at least one NAND die to be dedicated for writing random data and other NAND dies to be dedicated for writing sequential data; configuring one of the NAND dies dedicated for writing the sequential data to include memory cells each of which is allowed to be used for storing a data stream having the maximum number of bits; configuring one of the NAND dies dedicated for writing the random data to include memory cells each of which is used for storing a data stream having the number of bits that is smaller the maximum number of the bits; and determining the total number of the bits of one of the data streams of the random data written by the NAND dies and accordingly reconfiguring the NAND dies.

Abstract: A method for accessing data by a solid state disk is provided, which includes steps of: configuring at least one NAND die to be dedicated for writing random data and other NAND dies to be dedicated for writing sequential data; configuring one of the NAND dies dedicated for writing the sequential data to include memory cells each of which is allowed to be used for storing a data stream having the maximum number of bits; configuring one of the NAND dies dedicated for writing the random data to include memory cells each of which is used for storing a data stream having the number of bits that is smaller the maximum number of the bits; and determining the total number of the bits of one of the data streams of the random data written by the NAND dies and accordingly reconfiguring the NAND dies.

Abstract: A system and a method for processing storage device occurring abnormal power interruption are provided. The method includes the following steps: (a) providing data to the storage device by a master controller; (b) outputting an address storing instruction from the master controller; (c) storing an address of a storage block in an address storage; (d) executing a program for accessing the data by the storage device; (e) determining whether the storage device is abnormally powered down by the master controller, if yes, performing step (f), and if not, performing step (g) after completing the execution of the program; (f) instructing an storage control circuit of the storage device to execute an error processing procedure on the storage block corresponding to the address by the master controller, and then performing step (a); (g) clearing the address stored in the address storage according to an instruction from the master controller.

Abstract: A storage apparatus and a storing method are provided. The storage apparatus includes one or more storage devices, an interface expander and a master controller. The storage device includes a storage module, a storage control circuit and a ready/busy pin. The storage control circuit outputs an operational state signal according to an operational state of the storage module through the ready/busy pin. The master controller outputs an interface signal to indicate the interface expander to provide the operational state signal. The interface expander detects the ready/busy pin of the storage device to receive and transmit the operational state signal from the storage device to the master controller according to the interface signal. The master controller determines whether the storage device is in a busy state or a ready state according to the operational state signal, and accordingly outputs a control signal to control operations of the storage devices.

Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.

Abstract: An exemplary method of error checking and correction applied in a multi-channel system, includes: performing error checking and correction encoding upon a first data packet of a first channel and a second data packet of a second channel, and generating a first horizontal error correction code and a second horizontal error correction code; performing error checking and correction encoding upon a first mixed data packet and a second mixed data packet, and generating a first vertical error correction code and a second vertical error correction code; and combining the first data packet, the first horizontal error correction code and the first vertical error correction code into the first encoded data packet of the first channel, and combining the second data packet, the second horizontal error correction code and the second vertical error correction code into the second encoded data packet of the second channel.

Abstract: A memory control method, including: writing a write-in data which has a logical address into a write-in cache buffer; generating a write-in address mapping table which maps the logical address of the data to a physical address of a main memory, and writing the write-in address mapping table into a cached data mapping table write buffer; writing the write-in data into the main memory according to the write-in address mapping table; and when an available storage space of the cached data mapping table write buffer is reduced to reach a predetermined threshold, writing the address mapping table in the cached data mapping table write buffer into the main memory, and storing a corresponding main memory write-in address mapping table into a global mapping table buffer.

Abstract: The present invention relates to a data scanning circuit and method. According to the present invention, a memory circuit stores a plurality of codes. Each of the code corresponds to a sub-rule. The memory circuit outputs at least first bit and at least second bit of each code, respectively, according to a first and a second data items. An operational circuit performs logic operations on the first and second bits, and produces an operated result. A decision circuit decides whether the input data satisfies the scanning rule according to the operated result.

Abstract: A packet forwarding mechanism using a packet map is disclosed. The method includes the packet map storing a packet forwarding information of each packet, where the packet map uses a single bit to indicate whether a packet is forwarding through a specific output port. In this way, the packet forwarding information can be stored in a very simple form such that less memory space is required for storing the packet forwarding information.

Abstract: An allocating method for a flash memory is disclosed. The allocating method includes the following steps: adjusting a preliminary data storage capacity corresponding to the flash memory for determining a real data storage capacity of the flash memory; adjusting a preliminary spare area capacity corresponding to the flash memory for determining a real spare area capacity of the flash memory, wherein a total capacity of the preliminary data storage capacity and the preliminary spare area capacity is equal to the total capacity of the real data storage capacity and the real spare area capacity; and allocating the real data storage capacity and the real spare area capacity to the flash memory, wherein the real data storage capacity stores data, and the real spare area capacity stores parity codes generated by an error codes correction algorithm performed upon the stored data in the real data storage capacity.

Abstract: A cache apparatus for increasing data accessing speed of a storage device includes: a non-volatile memory, for storing data; a memory controller, coupled to the non-volatile memory, for controlling data accessing operations of the non-volatile memory; a first transmission interface, coupled to the memory controller, for electrically connecting the memory controller to the storage device; and a second transmission interface, coupled to the memory controller, for electrically connecting the memory controller to a user-end personal computer.

Abstract: A memory apparatus includes a non-volatile memory and a memory controller, where the memory controller is coupled to the non-volatile memory and is utilized for accessing the non-volatile memory, and the memory controller and the non-volatile memory are positioned in two independent chips, respectively. When external data is intended to be written into the non-volatile memory, the memory controller compresses the external data and stores compressed external data into the non-volatile memory.

Abstract: An allocating method for a flash memory is disclosed. The allocating method includes the following steps: adjusting a preliminary data storage capacity corresponding to the flash memory for determining a real data storage capacity of the flash memory; adjusting a preliminary spare area capacity corresponding to the flash memory for determining a real spare area capacity of the flash memory, wherein a total capacity of the preliminary data storage capacity and the preliminary spare area capacity is equal to the total capacity of the real data storage capacity and the real spare area capacity; and allocating the real data storage capacity and the real spare area capacity to the flash memory, wherein the real data storage capacity stores data, and the real spare area capacity stores parity codes generated by an error codes correction algorithm performed upon the stored data in the real data storage capacity.

Abstract: A flash memory circuit has both SATA and USB interfaces. When the flash memory circuit is coupled to a computer, the flash memory circuit utilizes the transmitted power from the computer through the USB interface for operating, and communicates with the computer through the faster SATA interface for data accessing of the flash memory.

Abstract: A packet forwarding mechanism using a packet map is disclosed. The method includes the packet map storing a packet forwarding information of each packet, where the packet map uses a single bit to indicate whether a packet is forwarding through a specific output port. In this way, the packet forwarding information can be stored in a very simple form such that less memory space is required for storing the packet forwarding information.

Abstract: The present invention relates to a data scanning circuit and method. According to the present invention, a memory circuit stores a plurality of codes. Each of the code corresponds to a sub-rule. The memory circuit outputs at least first bit and at least second bit of each code, respectively, according to a first and a second data items. An operational circuit performs logic operations on the first and second bits, and produces an operated result. A decision circuit decides whether the input data satisfies the scanning rule according to the operated result.

Abstract: A network device and a transmission method thereof are disclosed. The network device consists of a first network device and a second network device. According to at least one command, the first network device generates serial command, inserts the serial command into gaps between packet data and transmits the serial command to the second network device while outputting those packet data to the second network device. In accordance with the serial command received, the second network device saves data in a register of the second network device. Therefore, the transmission circuit is simplified, heat dissipation efficiency is improved and accuracy of signal transmission is ensured. Moreover, data in the register is retrieved precisely.

Abstract: A search method for a range search with a plurality of pre-set rules constructs a rule mapping table by dividing data associated with the rules into a plurality of sub-keys and generating output tables for each sub-key. A rule column is formed for a rule by following through each sub-key based on the associated range of data. A first output table for the first sub-key and upper and lower output tables are generated for each remaining sub-key. All the rule columns are arranged in parallel to form the rule mapping table. The method of search is accomplished by dividing an input data into a plurality of sub-keys and each sub-key is used to search through the rule mapping table for determining a rule that is satisfied with the input data. If multiple rules are satisfied, a priority encoder selects a highest priority rule as the search result.

Abstract: A flexible and high-performance packet classification algorithm. The algorithm includes converting the original rule database into rule mapping table format for storage. The method of producing the rule mapping table includes partitioning an input key into a plurality of sub-keys, and sequentially comparing various grouping combinations of each sub-key with the same sub-key field of each rule. Finally, the results are stored in the rule mapping table using a bit-map method. This invention provides a packet classification algorithm that support a plurality of rule databases or sub-tables such that the co-existence of a plurality of rule databases each having a different length and width in the same search engine is permitted. In addition, the design can provide actual improvements (higher speed, smaller volume occupation) and flexibility (possible coexistent of different rule databases).