Patents by Inventor Kuo-Hwa Tzeng
Kuo-Hwa Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10204822Abstract: In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.Type: GrantFiled: January 30, 2018Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Publication number: 20180308928Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung CHENG, Yong-En SYU, Kuo-Hwa TZENG, Ke-Dian WU, Cheng-Ta WU, Yeur-Luen TU, Ming-Che YANG, Wei-Kung TSAI
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Publication number: 20180174888Abstract: In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.Type: ApplicationFiled: January 30, 2018Publication date: June 21, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien CHOU, Hung-Ling SHIH, Tsun-Kai TSAO, Ming-Huei SHEN, Kuo-Hwa TZENG, Yeur-Luen TU
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Patent number: 9917003Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.Type: GrantFiled: June 28, 2013Date of Patent: March 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Patent number: 9281331Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.Type: GrantFiled: June 19, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chau Chen, Chih-Yu Lai, Kuo-Ming Wu, Kuo-Hwa Tzeng, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 9245792Abstract: Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the etch stop layer. The etch stop layer is patterned through a first photolithography and etch process to form openings in the etch stop layer, prior to the formation of the trench dielectric layer. A second photolithography and etch process is performed after formation of the trench dielectric layer to create trench openings in the trench dielectric layer and via openings in the via dielectric layer, where the patterned etch stop layer acts as a hard-mask in forming vias in the via dielectric layer.Type: GrantFiled: July 25, 2008Date of Patent: January 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Publication number: 20150372034Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.Type: ApplicationFiled: June 19, 2014Publication date: December 24, 2015Inventors: Sheng-Chau Chen, Chih-Yu Lai, Kuo-Ming Wu, Kuo-Hwa Tzeng, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 9159808Abstract: A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.Type: GrantFiled: November 12, 2009Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Publication number: 20150001669Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
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Patent number: 8546242Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.Type: GrantFiled: May 25, 2012Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Chih-Hsiang Chang, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Patent number: 8319311Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate.Type: GrantFiled: January 18, 2010Date of Patent: November 27, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Cheng-Yuan Tsai, Kuo-Hwa Tzeng
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Publication number: 20120235273Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.Type: ApplicationFiled: May 25, 2012Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Chih-Hsiang Chang, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Patent number: 8187948Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.Type: GrantFiled: February 18, 2008Date of Patent: May 29, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Chih-Hsiang Chang, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Patent number: 8173516Abstract: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer.Type: GrantFiled: February 11, 2010Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Publication number: 20110195559Abstract: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer.Type: ApplicationFiled: February 11, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Patent number: 7892929Abstract: A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.Type: GrantFiled: July 15, 2008Date of Patent: February 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai, Jeffrey Junhao Xu
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Publication number: 20100230757Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate.Type: ApplicationFiled: January 18, 2010Publication date: September 16, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Cheng-Yuan Tsai, Kuo-Hwa Tzeng
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Publication number: 20100190345Abstract: A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.Type: ApplicationFiled: November 12, 2009Publication date: July 29, 2010Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Patent number: 7655532Abstract: A method of forming a shallow trench isolation region includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; filling a precursor into the opening using spin-on; performing a steam cure to the precursor to generate a dielectric material; after the steam cure, performing a chemical mechanical polish (CMP) to the dielectric material; and after the CMP, performing a steam anneal to the dielectric material.Type: GrantFiled: July 25, 2008Date of Patent: February 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Publication number: 20100022084Abstract: Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the etch stop layer. The etch stop layer is patterned through a first photolithography and etch process to form openings in the etch stop layer, prior to the formation of the trench dielectric layer. A second photolithography and etch process is performed after formation of the trench dielectric layer to create trench openings in the trench dielectric layer and via openings in the via dielectric layer, where the patterned etch stop layer acts as a hard-mask in forming vias in the via dielectric layer.Type: ApplicationFiled: July 25, 2008Publication date: January 28, 2010Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai