Patents by Inventor Kuo Hwang

Kuo Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11519962
    Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: December 6, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jeong-Fa Sheu, Chen-Kuo Hwang, Mei-Chuan Lu, Wei-Chung Cho
  • Publication number: 20220283222
    Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.
    Type: Application
    Filed: August 24, 2021
    Publication date: September 8, 2022
    Inventors: Jeong-Fa SHEU, Chen-Kuo HWANG, Mei-Chuan LU, Wei-Chung CHO
  • Patent number: 11115738
    Abstract: A bandwidth allocation device includes a buffer device, a main scheduler, an oversubscription scheduler, a multiplexer and a detecting device. The buffer device is arranged to receive first data units from first ports and second data units from second ports and accordingly output these data units. The main scheduler is configured to schedule the first data units and accordingly output the first data units in sequence. The oversubscription scheduler is configured to schedule the second data units and accordingly output the second data units in sequence. The multiplexer is controlled by the main scheduler to select the first data units outputted by the main scheduler and the second data units outputted by the oversubscription scheduler for outputting. The detecting device is arranged to generate power-related information which the main scheduler relies on to control the multiplexer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 7, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chen-Kuo Hwang, Yung-Chang Lin, Chih-Hao Wang
  • Publication number: 20210258667
    Abstract: A bandwidth allocation device includes a buffer device, a main scheduler, an oversubscription scheduler, a multiplexer and a detecting device. The buffer device is arranged to receive first data units from first ports and second data units from second ports and accordingly output these data units. The main scheduler is configured to schedule the first data units and accordingly output the first data units in sequence. The oversubscription scheduler is configured to schedule the second data units and accordingly output the second data units in sequence. The multiplexer is controlled by the main scheduler to select the first data units outputted by the main scheduler and the second data units outputted by the oversubscription scheduler for outputting. The detecting device is arranged to generate power-related information which the main scheduler relies on to control the multiplexer.
    Type: Application
    Filed: May 18, 2020
    Publication date: August 19, 2021
    Inventors: Chen-Kuo Hwang, Yung-Chang Lin, Chih-Hao Wang
  • Patent number: 10931787
    Abstract: A method of forwarding information base synchronization for a network switch stacking system includes transmitting by at least one slave network switch at least one change event to a master network switch, generating by the master network switch a change confirmation to the at least one slave network switch when a master forwarding information base is determined to be necessarily updated by the master network switch according to the at least one change event, and updating by the at least one slave network switch at least one slave forwarding information base according to the change confirmation, wherein the at least one change event includes at least one of a new learn event, a port move event, a regular port aging out event, a logic aggregation update aging time event.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 23, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chen-Kuo Hwang, Jui-Chang Tsao
  • Patent number: 10693478
    Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 23, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jui-Chang Tsao, Chen-Kuo Hwang, Po-Wei Liu
  • Publication number: 20200076921
    Abstract: A method of forwarding information base synchronization for a network switch stacking system includes transmitting by at least one slave network switch at least one change event to a master network switch, generating by the master network switch a change confirmation to the at least one slave network switch when a master forwarding information base is determined to be necessarily updated by the master network switch according to the at least one change event, and updating by the at least one slave network switch at least one slave forwarding information base according to the change confirmation, wherein the at least one change event includes at least one of a new learn event, a port move event, a regular port aging out event, a logic aggregation update aging time event.
    Type: Application
    Filed: March 26, 2019
    Publication date: March 5, 2020
    Inventors: Chen-Kuo Hwang, Jui-Chang Tsao
  • Publication number: 20200052707
    Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 13, 2020
    Inventors: Jui-Chang TSAO, Chen-Kuo Hwang, Po-Wei LIU
  • Publication number: 20070157834
    Abstract: A method for producing a stamp with a pattern includes deciding a design, the design including three sections separated by three imaginary lines that intersect with one another at a common imaginary point, the design being distributed in the three sections and exhibiting a three-dimensional visual effect; and processing an end of a stamp to form a pattern according to the design, with the pattern exhibiting a three-dimensional visual effect. The stamp includes a body with an end face. The end face includes a pattern having three sections separated by three imaginary lines that intersect with one another at a common imaginary point. The pattern exhibits a three-dimensional visual effect.
    Type: Application
    Filed: January 10, 2006
    Publication date: July 12, 2007
    Inventor: Kuo Hwang
  • Publication number: 20060286413
    Abstract: A magnetic recording medium having a substrate, a granular magnetic layer and a magnetic cap layer covered with carbon overcoat, in this order, wherein both the granular magnetic and magnetic cap layers contain magnetic grains and non-magnetic grain boundaries, and further wherein the magnetic cap layer has denser grain boundaries and the magnetic cap layer contains substantially no oxide is disclosed. The magnetic cap layer serves as both magnetic layer and corrosion barrier for lower HMS.
    Type: Application
    Filed: June 17, 2005
    Publication date: December 21, 2006
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Connie Liu, Xiaoding Ma, Qixu Chen, Shanghsien Rou, Mariana Munteanu, Miaogen Lu, Michael Wu, Kueir-Weei Chour, Kuo Hwang
  • Publication number: 20060246323
    Abstract: A magnetic recording medium having a substrate, a first magnetic layer having a perpendicular anisotropy and a second magnetic layer having a perpendicular anisotropy, wherein the second magnetic layer contains substantially no dielectric material, (such as, but not limited to, oxides, carbides, and nitrides) is disclosed. Also disclosed is a method for manufacturing the magnetic recording medium of the embodiments of this invention.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 2, 2006
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Connie Liu, Qixu Chen, Shanghsien Rou, Kueir-Weei Chour, Romulo Ata, Kuo Hwang
  • Patent number: 4869903
    Abstract: A method of inhibiting HIV replication in and cellular proliferation of HIV-infected cells. The infected cells are exposed to a single-chain ribosome inactivating protein, at a protein concentration and for an exposure period sufficient to produce a substantial reduction in (a) the level of HIV antigen or reverse transcriptase associated with the infected cells, (b) the ratio of viability of infected/uninfected T cells, and/or (c) the ratio of HIV antigen/cellular antigen in infected macrophages. The method is used to treat HIV infection in humans.
    Type: Grant
    Filed: April 8, 1988
    Date of Patent: September 26, 1989
    Assignee: Genelabs Incorporated
    Inventors: Jeffrey D. Lifson, Michael S. McGrath, Hin-Wing Yeung, Kuo Hwang