Patents by Inventor Kuo Jen HUANG

Kuo Jen HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186700
    Abstract: An antenna system includes a signal feeding element, a first transmission line, a second transmission line, a first antenna element, a second antenna element, and a reflective plane. The first antenna element includes a first radiation element and a second radiation element. The second antenna element includes a third radiation element and a fourth radiation element. Each of the first radiation element, the second radiation element, the third radiation element, and the fourth radiation element includes a main branch, a first branch, and a second branch. The main branch has a first end and a second end. The first branch is coupled to the first end of the main branch. The second branch is coupled to the second end of the main branch. A slot region is surrounded by the main branch, the first branch, and the second branch.
    Type: Application
    Filed: November 7, 2023
    Publication date: June 6, 2024
    Inventors: Chin-Lien HUANG, Chun-Jui PAN, Kuo-Jen LAI
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240079524
    Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
  • Publication number: 20230098236
    Abstract: Robust estimation of temperatures inside and outside a device can be achieved using one or more absolute temperature sensors optionally in conjunction with thermopile heat flux sensors. Thermopile temperature sensing systems can measure a temperature gradient across two locations within the device, to estimate absolute temperature at locations that are impractical to measure using absolute temperature sensors. Using heat flux models associated with the device, the thermopile temperature sensing system can be used to estimate temperature associated with objects that contact an outer surface of the device, such as a user's skin temperature. Additionally, the thermopile temperature sensing system can be used to estimate ambient air temperature. Within a device, temperature measurements from the thermopile temperature sensors can be used to compensate sensor measurements, such as when the accuracy or reliability of a sensor varies with temperature.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 30, 2023
    Inventors: Wegene H. TADELE, Habib S. KARAKI, James C. CLEMENTS, Chin S. HAN, Craig C. D'SOUZA, Daniel W. LABOVE, Esther CHEN, Joseph R. LEE, Kuo Jen HUANG, Wanfeng HUANG, Fred Y. CHOU, Hongling CHENG, Ali M. AMIN, Chia-Hsien LIN