Patents by Inventor Kuo-Ji Chen

Kuo-Ji Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149077
    Abstract: An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Tian-Yu XIE, Xin-Yong WANG, Lei PAN, Kuo-Ji CHEN
  • Publication number: 20220139903
    Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tao-Yi HUNG, Wun-Jie LIN, Jam-Wem LEE, Kuo-Ji CHEN, Chia-En HUANG
  • Publication number: 20220045052
    Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Jam-Wem Lee, Kuo-Ji Chen, Kuan-Lun Cheng
  • Publication number: 20220037365
    Abstract: An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 3, 2022
    Inventors: Chien Yao HUANG, Wun-Jie LIN, Kuo-Ji CHEN
  • Patent number: 11239255
    Abstract: An IC structure includes first and second transistors, an isolation region and a first gate extension. The first transistor includes a first gate and first source/drain regions respectively on opposite sides of the first gate. The second transistor includes a second gate and second source/drain regions respectively on opposite sides of the second gate. The isolation region is laterally between the first and second transistors. A first one of the first source/drain regions has a first source/drain extension protruding from a first boundary of the isolation region, and a first one of the second source/drain regions has a second source/drain extension protruding from a second boundary of the isolation region. The first gate extension extends from the first gate to a position overlapping the isolation region.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: February 1, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Tian-Yu Xie, Xin-Yong Wang, Lei Pan, Kuo-Ji Chen
  • Patent number: 11211376
    Abstract: An integrated circuit includes two or more substrates stacked one over another and a first set of electrical components on one or more of the two or more substrates. The two or more substrates include a first substrate having a first predetermined doping type and a second substrate having the first predetermined doping type. The first set of electrical components is configured to form a first circuit. The integrated circuit further includes a first ground reference rail electrically connected to the first circuit, a first common ground reference rail, and a first ESD conduction element electrically connected between the first ground reference rail and the first common ground reference rail. The first ESD conduction element includes a first diode on the first substrate and a second diode on the second substrate. The first diode and the second diode are electrically connected in parallel and have opposite polarities.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Yu Ma, Chia-Hui Chen, Kuo-Ji Chen
  • Publication number: 20210366846
    Abstract: A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails.
    Type: Application
    Filed: March 26, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Tao Yi Hung, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin
  • Patent number: 11158634
    Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Jam-Wem Lee, Kuo-Ji Chen, Kuan-Lun Cheng
  • Publication number: 20210272984
    Abstract: An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.
    Type: Application
    Filed: September 17, 2020
    Publication date: September 2, 2021
    Inventors: Chien Yao HUANG, Wun-Jie LIN, Kuo-Ji CHEN
  • Publication number: 20210257316
    Abstract: A method includes forming signal lines in a pair of neighboring metal layers of a semiconductor device, and forming first dummy conductive cells in an empty area without metal lines passing therethrough, between the pair of neighboring metal layers. At least two dummy conductive cells of the first dummy conductive cells that are separated from each other, and the at least two dummy conductive cells fully overlap one of the signal lines in plan view.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 19, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu MA, Hui-Mei CHOU, Kuo-Ji CHEN
  • Publication number: 20210193647
    Abstract: An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Wei Yu MA, Chia-Hui CHEN, Kuo-Ji CHEN
  • Publication number: 20210175707
    Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Inventors: Po-Hung Chen, Kuo-Ji Chen, Shao-Yu Chou
  • Patent number: 10991663
    Abstract: A method is disclosed and includes forming a plurality of dummy conductive cells that provides different densities in empty areas in metal layers of a semiconductor device according to overlap conditions of the empty areas each arranged between a pair of neighboring metal layers of metal layers. Forming the plurality of dummy conductive cells includes operations of forming a group of dummy conductive cells in a single empty area of the empty areas when the single empty area in one pair of the neighboring metal layers is overlapped by a signal line in the same pair of the neighboring metal layers. When viewed in plan view, projection areas of the group of dummy conductive cells are vertically overlapped by a projection area of the signal line. A semiconductor device is also disclosed herein.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Ma, Hui-Mei Chou, Kuo-Ji Chen
  • Publication number: 20210117605
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 22, 2021
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Publication number: 20210091176
    Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 25, 2021
    Inventors: Wan-Yen LIN, Wun-Jie LIN, Yu-Ti SU, Bo-Ting CHEN, Jen-Chou TSENG, Kuo-Ji CHEN, Sun-Jay CHANG, Min-Chang LIANG
  • Patent number: 10943897
    Abstract: A method (of forming an integrated circuit) includes: forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type; forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed on the first substrate, and the second substrate having the first predetermined doping type; and forming conductive paths electrically connecting the first diode 3A and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Yu Ma, Chia-Hui Chen, Kuo-Ji Chen
  • Patent number: 10931103
    Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hung Chen, Kuo-Ji Chen, Shao-Yu Chou
  • Patent number: 10872190
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 22, 2020
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 10868112
    Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Publication number: 20200365579
    Abstract: A device includes first and second standard cells in a layout of an integrated circuit, and first and second active regions. The first standard cell includes an electrostatic discharge (ESD) protection unit, and the second standard cell includes first and second transistors that connect to the ESD protection unit. The first active region includes first, second, and third source/drain regions. The first standard cell includes a first gate arranged across the first active region; and a second gate that is separated from the first gate and is arranged across the first active region and the second active region. The first gate, the first source/drain region and the second source/drain region together correspond to a third transistor of the ESD protection unit. The second gate, the second source/drain region and the third source/drain region together correspond to the first transistor.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Heng CHANG, Kuo-Ji CHEN, Ming-Hsiang SONG