Patents by Inventor Kuo-Ji Chen
Kuo-Ji Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9082623Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.Type: GrantFiled: December 16, 2013Date of Patent: July 14, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Yi Yang, Kuo-Ji Chen, Chien-Yuan Lee
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Publication number: 20150171074Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Yi Yang, Kuo-Ji Chen, Chien-Yuan Lee
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Patent number: 9035393Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.Type: GrantFiled: February 28, 2013Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Yu Ma, Bo-Ting Chen, Ting Yu Chen, Kuo-Ji Chen, Li-Chun Tien
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Patent number: 9026973Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.Type: GrantFiled: May 7, 2013Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Chun Tien, Chen-Chi Wu, Kuo-Ji Chen
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Publication number: 20150118809Abstract: A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor.Type: ApplicationFiled: January 9, 2015Publication date: April 30, 2015Inventors: Harry-Hak-Lay CHUANG, Ming-Hsiang SONG, Kuo-Ji CHEN, Ming ZHU, Po-Nien CHEN, Bao-Ru YOUNG
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Publication number: 20150115419Abstract: A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a plurality of empty areas in a plurality of metal layers of a semiconductor device according to overlap conditions of the empty areas between each pair of neighboring metal layers.Type: ApplicationFiled: October 24, 2013Publication date: April 30, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu MA, Hui-Mei CHOU, Kuo-Ji CHEN
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Publication number: 20150077886Abstract: A device includes a first power transistor, a second power transistor electrically connected in series with the first power transistor, a first electrostatic discharge (ESD) detection circuit, and a first control circuit electrically connected to the first ESD detection circuit and the first power transistor.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hui Chen, Po-Hsiang Lan, Chien-Yuan Lee, Tsung-Ju Yang, Tzu-Yi Yang, Kuo-Ji Chen
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Publication number: 20150062761Abstract: A circuit, a multiple power domain circuit, and a method are disclosed. An embodiment is a circuit including an input circuit having a first output and a second output, the input circuit being coupled to a first power supply voltage, and a level-shifting circuit having a first input coupled to the first output of the input circuit and a second input coupled to the second output of the input circuit, the level-shifting circuit being coupled to a second power supply voltage. The circuit further includes a first transistor coupled between a first node of the level-shifting circuit and the second power supply voltage, and a control circuit having an output coupled to a gate of the first transistor, the control circuit being coupled to the second power supply voltage.Type: ApplicationFiled: September 19, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hui Chen, Chia-Hung Chu, Kuo-Ji Chen, Ming-Hsiang Song, Lee-Chung Lu
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Patent number: 8940596Abstract: A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region.Type: GrantFiled: October 21, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Ming-Hsiang Song, Kuo-Ji Chen, Ming Zhu, Po-Nien Chen, Bao-Ru Young
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Patent number: 8943454Abstract: In some embodiments, in a method for considering in-phase grouping for a voltage-dependent design rule, for a first net and a second net in a schematic, first data for obtaining the differences between first voltage values of the first and second nets, and between second voltage values of the first and second nets is provided. For each of the first and second nets, the first voltage value is larger than the second voltage value. A layout for the schematic is generated. In the layout, a relationship of a first shape and a second shape associated with the first and the second nets, respectively, is defined using the first data.Type: GrantFiled: November 5, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chih Chi Hsiao, Jill Liu, Wei-Yi Hu, Jui-Feng Kuan, Yu-Ren Chen, Kuo-Ji Chen, Jian-Yi Li, Wen-Ju Yang
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Publication number: 20140268449Abstract: A device includes a first power node, a second power node, a first input node, a second input node, a protected circuit, and a switch circuit. The protected circuit is coupled between the first power node and the second power node, and the protected circuit is further coupled with the second input node. The switch circuit is coupled with the first power node, the second power node, the first input node, and the second input node. The switch circuit is configured to electrically decouple the first input node and the second input node after (a) the first power node is floating or electrically coupled to the second power node and (b) a voltage level at the first input node is greater than a voltage level at the second power node by a predetermined voltage value.Type: ApplicationFiled: August 30, 2013Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hung CHU, Kuo-Ji CHEN
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Publication number: 20140264894Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.Type: ApplicationFiled: May 7, 2013Publication date: September 18, 2014Inventors: Li-Chun TIEN, Chen-Chi WU, Kuo-Ji CHEN
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Publication number: 20140210014Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.Type: ApplicationFiled: February 28, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Yu MA, Bo-Ting CHEN, Ting Yu CHEN, Kuo-Ji CHEN, Li-Chun TIEN
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Patent number: 8743515Abstract: Some embodiments relate to an area efficient electrostatic discharge (ESD) clamp comprising an RC trigger circuit, having one or more low-voltage, thin-oxide devices, which is configured to operate with a high-voltage power supply. In some embodiments, the ESD clamp comprises an RC trigger circuit connected between a first circuit node having a first voltage and a second circuit node having a second voltage. The RC trigger circuit comprises a resistive element connected in series with a thin-oxide MOS capacitor. The MOS capacitor has a source and drain connected to an intermediate supply voltage between the first and second voltage, and a body connected to the second voltage. By connecting the source and drain to the intermediate supply voltage, the thin-oxide MOS capacitor is able to reliably operate with a high-voltage power supply.Type: GrantFiled: January 13, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Yi Yang, Kuo-Ji Chen
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Publication number: 20140045310Abstract: A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay CHUANG, Ming-Hsiang SONG, Kuo-Ji CHEN, Ming ZHU, Po-Nien CHEN, Bao-Ru YOUNG
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Publication number: 20140042590Abstract: Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Ji Chen, Wen-Chuan Chiang, Huey-Chi Chu, Ming-Hsiang Song, Chen-Jong Wang
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Patent number: 8648425Abstract: A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.Type: GrantFiled: June 28, 2011Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Han Wang, Chen-Chih Wu, Sheng-Fang Cheng, Kuo-Ji Chen
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Publication number: 20130342941Abstract: Some embodiments of the present disclosure relate to a low-power, area efficient ESD protection device that provides ESD protection to an ESD susceptible circuit. The ESD protection device has a trigger circuit with a resistor. The resistor has a first terminal connected to the first external pin and a second terminal connected directly to a gate of a SiGe based PMOS shunt transistor. The trigger circuit generates a trigger signal that drives the gate of the PMOS device to shunt power away from the ESD susceptible circuit when an ESD event is present. The SiGe based PMOS shunt transistor has a lower gate leakage than a conventional NMOS shunt transistors, thereby providing for an ESD circuit with a low leakage current at small gate lengths.Type: ApplicationFiled: June 26, 2012Publication date: December 26, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Han Wang, Kuo-Ji Chen
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Patent number: 8587074Abstract: A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed.Type: GrantFiled: May 5, 2011Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Ming-Hsiang Song, Kuo-Ji Chen, Ming Zhu, Po-Nien Chen, Bao-Ru Young
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Publication number: 20130182356Abstract: Some embodiments relate to an area efficient electrostatic discharge (ESD) clamp comprising an RC trigger circuit, having one or more low-voltage, thin-oxide devices, which is configured to operate with a high-voltage power supply. In some embodiments, the ESD clamp comprises an RC trigger circuit connected between a first circuit node having a first voltage and a second circuit node having a second voltage. The RC trigger circuit comprises a resistive element connected in series with a thin-oxide MOS capacitor. The MOS capacitor has a source and drain connected to an intermediate supply voltage between the first and second voltage, and a body connected to the second voltage. By connecting the source and drain to the intermediate supply voltage, the thin-oxide MOS capacitor is able to reliably operate with a high-voltage power supply.Type: ApplicationFiled: January 13, 2012Publication date: July 18, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Yi Yang, Kuo-Ji Chen