Patents by Inventor Kuo-Ju Chen

Kuo-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098365
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Application
    Filed: March 2, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Publication number: 20210082894
    Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
  • Patent number: 10950729
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
  • Patent number: 10950694
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Maio Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20210066500
    Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.
    Type: Application
    Filed: May 21, 2020
    Publication date: March 4, 2021
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
  • Publication number: 20200402853
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure. The semiconductor structure also includes a source/drain structure in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a first contact plug over the source/drain structure. The semiconductor structure also includes a first via plug over the first contact plug. The semiconductor structure also includes a dielectric layer surrounding the first via plug. The first via plug includes a first group IV element and the dielectric layer includes the first group IV element and a second group IV element.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Po HSIEH, Su-Hao LIU, Hong-Chih LIU, Jing-Huei HUANG, Jie-Huang HUANG, Lun-Kuang TAN, Huicheng CHANG, Liang-Yin CHEN, Kuo-Ju CHEN
  • Patent number: 10868178
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Publication number: 20200350113
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: Feng-Lung CHIEN, Tsang-Feng WU, Yuan HAN, Tzu-Chieh KAO, Chien-Hung LIN, Kuang-Lun LEE, Hsiang-Hui HSU, Shu-Yi TSUI, Kuo-Jui LEE, Kun-Ying LEE, Mao-Chun CHEN, Tai-Hsien YU, Wei-Yu CHEN, Yi-Ju LI, Kuei-Yuan CHANG, Wei-Chun LI, Ni-Ni LAI, Sheng-Hao LUO, Heng-Sheng PENG, Yueh-Hui KUAN, Hsiu-Chen LIN, Yan-Bing ZHOU, Chris T. Burket
  • Patent number: 10766922
    Abstract: A compound and pharmaceutically acceptable salts thereof for treating cancer, having a structure represented by the following formula (I) or formula (II): in which X and Y each individually represent: R1, R2, R3, R4, and R5 individually represents hydrogen atom, acyl having 20 or less carbon atoms, alkyl having 20 or less carbon atoms, alkanoyl having 20 or less carbon atoms, aroyl having 20 or less carbon atoms, aryl having 20 or less carbon atoms, aralkyl having 20 or less carbon atoms, sulfonyl having 20 or less carbon atoms, phosphonyl having 20 or less carbon atoms, or haloacyl having 20 or less carbon atoms.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 8, 2020
    Assignee: AQUAVAN TECHNOLOGY CO., LTD.
    Inventors: Kuo-Tang Tseng, Hsin Ju Wang, Wen-Hung Chen
  • Publication number: 20200279944
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Patent number: 10763168
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jing-Huei Huang, Jie-Huang Huang, Lun-Kuang Tan, Huicheng Chang, Liang-Yin Chen, Kuo-Ju Chen
  • Publication number: 20200266299
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an epitaxial structure over a semiconductor substrate. The method also includes generating and applying plasma on an entire exposed surface of the epitaxial structure to form a modified region in the epitaxial structure. The plasma is directly applied on the source/drain structure without being filtered out, and the plasma includes ions with different charges. The method further includes forming a metal layer on the modified region and heating the metal layer and the modified region to form a metal-semiconductor compound region.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng CHEN, Su-Hao LIU, Kuo-Ju CHEN, Liang-Yin CHEN
  • Patent number: 10658508
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen
  • Patent number: 10658510
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Patent number: 10643892
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20200135912
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Yi-Ju CHEN, Jyh-Huei CHEN
  • Publication number: 20200126857
    Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.
    Type: Application
    Filed: January 31, 2019
    Publication date: April 23, 2020
    Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
  • Publication number: 20200119195
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Patent number: 10606046
    Abstract: A zoom lens arranged along an optical axis includes a first lens group and a second lens group. The second lens group has at least one aspheric lens. The first lens group moves toward an image side and the second lens group moves away from the image side along the optical axis during zooming. The first lens group is moved for focusing, and the second lens group is moved for zooming.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 31, 2020
    Assignee: Young Optics Inc.
    Inventors: Kuo-Chuan Wang, Bing-Ju Chiang, Pin-Hsuan Hsieh, Kai-Yun Chen, Yu-Hung Chou
  • Patent number: 10564398
    Abstract: A lens including a first lens group and a second lens group is provided. The first lens group is disposed between a magnified side and a minified side. The second lens group is disposed between the first lens group and the minified side. The lens includes six or less lens elements, and at least four of the six or less lens elements are aspheric lenses. A field of view of the lens is in a range between 100 degrees and 165 degrees, and the second lens group has at least one spherical lens.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 18, 2020
    Assignee: Rays Optics Inc.
    Inventors: Bing-Ju Chiang, Hsin-Te Chen, Kuo-Chuan Wang, Sheng-Da Jiang