Patents by Inventor Kuo-Ju Chen
Kuo-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250126874Abstract: A method includes a number of operations. An interlayer dielectric (ILD) layer is formed over a source/drain region on a substrate. A source/drain contact extending through the ILD layer to electrically connect with the source/drain region is formed. An air gap extending through the ILD layer is formed. An implantation energy absorption dielectric layer is formed over the ILD layer. An implantation process is performed on the implantation energy absorption dielectric layer, wherein the implantation process causes the ILD layer expands to seal the air gap. A first implant-free dielectric layer is formed over the implantation energy absorption dielectric layer. A second implant-free dielectric layer is formed over the first implant-free dielectric layer. A source/drain via extending through the second implant-free dielectric layer, the first implant-free dielectric layer, and the implantation energy absorption dielectric layer to the source/drain contact is formed.Type: ApplicationFiled: October 16, 2023Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ju CHEN, Te-Jui YEN, Liang-Yin CHEN, Chi On CHUI
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Patent number: 12278141Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.Type: GrantFiled: February 18, 2022Date of Patent: April 15, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Meng-Han Chou, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250096041Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.Type: ApplicationFiled: November 21, 2024Publication date: March 20, 2025Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12243940Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.Type: GrantFiled: June 16, 2023Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
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Patent number: 12224327Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.Type: GrantFiled: August 7, 2023Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12183632Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.Type: GrantFiled: July 26, 2022Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Chou, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240395606Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240387661Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240363399Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Inventors: Kuo-Ju Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Meng-Han Chou
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Patent number: 12112977Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.Type: GrantFiled: March 27, 2023Date of Patent: October 8, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Ju Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Meng-Han Chou
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Publication number: 20240321751Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.Type: ApplicationFiled: May 3, 2024Publication date: September 26, 2024Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12068195Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: GrantFiled: June 7, 2023Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Publication number: 20240274527Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.Type: ApplicationFiled: March 26, 2024Publication date: August 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
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Publication number: 20240250147Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.Type: ApplicationFiled: April 2, 2024Publication date: July 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12015055Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: GrantFiled: July 12, 2023Date of Patent: June 18, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Patent number: 12009305Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.Type: GrantFiled: April 18, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11984491Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.Type: GrantFiled: June 27, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240154010Abstract: Embodiments of the present disclosure relates to a semiconductor device structure. The structure includes a source/drain epitaxial feature disposed over a substrate, a first interlayer dielectric (ILD) disposed over the source/drain epitaxial feature, a second ILD disposed over the first ILD. The second ILD includes a first dopant species having an atomic radius equal to or greater than silicon and a second dopant species having an atomic mass less than 15. The structure also includes a first conductive feature disposed in the second ILD, and a second conductive feature disposed over the source/drain epitaxial feature, the second conductive feature extending through the first ILD and in contact with the first conductive feature.Type: ApplicationFiled: January 22, 2023Publication date: May 9, 2024Inventors: Meng-Han Chou, Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240145596Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
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Patent number: 11973027Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.Type: GrantFiled: March 23, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho