Patents by Inventor Kuo-Kai Hsieh

Kuo-Kai Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Autonomous hardware for application power usage optimization
    Patent number: 10481674
    Abstract: Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: November 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jayanta Bhadra, Wen Chen, Monica Farkash, Kuo-Kai Hsieh
  • AUTONOMOUS HARDWARE FOR APPLICATION POWER USAGE OPTIMIZATION
    Publication number: 20180024614
    Abstract: Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.
    Type: Application
    Filed: July 20, 2016
    Publication date: January 25, 2018
    Inventors: Jayanta Bhadra, Wen Chen, Monica C. Farkash, Kuo-Kai Hsieh