Abstract: An active device substrate includes a substrate, a first thin film transistor located above the substrate and a second thin film transistor located above the substrate. The first thin film transistor includes a first metal oxide layer, a first gate, a first source and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The second thin film transistor includes a second metal oxide layer, a second gate, a second source and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to a same patterned layer.

Abstract: An active device substrate includes a substrate, an active device and a barrier layer. The active device is located on the substrate. The barrier layer is located on the active device. The barrier layer includes a first hydrogen atom distribution region and a second hydrogen atom distribution region. The first hydrogen atom distribution region includes silicon nitride and hydrogen atom. The first hydrogen atom distribution region is located between the second hydrogen atom distribution region and the substrate. The second hydrogen atom distribution region includes silicon nitride and hydrogen atom. The concentration of nitrogen atom in the first hydrogen atom distribution region is less than the concentration of nitrogen atom in the second hydrogen atom distribution region. The highest concentration of hydrogen atom in the first hydrogen atom distribution region is greater than the highest concentration of hydrogen atom in the second hydrogen atom distribution region.

Abstract: A light emitting device including a base, a first electrode, a barrier structure layer, a light emitting layer and a second electrode is provided. The barrier structure layer includes a first barrier layer in contact with the first electrode, a second barrier layer and a third barrier layer. The first barrier layer, the second barrier layer and the third barrier layer stack sequentially. The materials of the first barrier layer and the third barrier layer include a dielectric material. The material of the second barrier layer includes a metal material. A boundary between the third barrier layer and the second barrier layer keeps a vertical distance from the first electrode. The light emitting structure layer is disposed between the first electrode and the second electrode and surrounded by the barrier structure layer. The thickness of the light emitting structure layer is not greater than the vertical distance.

Abstract: A light emitting device including a base, a first electrode, a barrier structure layer, a light emitting layer and a second electrode is provided. The barrier structure layer includes a first barrier layer in contact with the first electrode, a second barrier layer and a third barrier layer. The first barrier layer, the second barrier layer and the third barrier layer stack sequentially. The materials of the first barrier layer and the third barrier layer include a dielectric material. The material of the second barrier layer includes a metal material. A boundary between the third barrier layer and the second barrier layer keeps a vertical distance from the first electrode. The light emitting structure layer is disposed between the first electrode and the second electrode and surrounded by the barrier structure layer. The thickness of the light emitting structure layer is not greater than the vertical distance.

Abstract: A thin film includes a substrate, a bottom gate, a channel layer, a source and a drain, and a top gate. The bottom gate is disposed on the substrate. The channel layer is disposed on the bottom gate. The source and the drain are disposed on two different sides of the channel layer. The top gate is disposed on the channel layer, wherein the channel layer is disposed between the bottom gate and the top gate, and the bottom gate and the top gate are electrically isolated from each other. A related method is also provided.

Abstract: A method of manufacturing an array substrate of a display is provided. The method includes forming a first bank material layer on a first substrate, wherein a material of the first bank material layer includes hydrophobic element; patterning the first bank material layer to form a first bank having at least one first concave; forming a first electrode on the first bank and in the first concave after the step of patterning the first bank material layer to form the first bank; and forming an color layer on the first electrode.

Abstract: A method of manufacturing an array substrate of a display is provided. The method includes forming a first bank material layer on a first substrate, wherein a material of the first bank material layer includes hydrophobic element; patterning the first bank material layer to form a first bank having at least one first concave; forming a first electrode on the first bank and in the first concave after the step of patterning the first bank material layer to form the first bank; and forming an color layer on the first electrode.

Abstract: A thin film includes a substrate, a bottom gate, a channel layer, a source and a drain, and a top gate. The bottom gate is disposed on the substrate. The channel layer is disposed on the bottom gate. The source and the drain are disposed on two different sides of the channel layer. The top gate is disposed on the channel layer, wherein the channel layer is disposed between the bottom gate and the top gate, and the bottom gate and the top gate are electrically isolated from each other. A related method is also provided.

Abstract: A method of signal identification, including: receiving a signal; utilizing a clock generated by a ring oscillator to sample the signal continuously to generate a plurality of sampled signals; counting each sampled signal length corresponding to successive sampled signals each having an identical value; and identifying a content of the signal according to a plurality of sampled signal lengths. A signal identification apparatus, including: a receiving circuit, arranged for receiving a signal; a ring oscillator, arranged for generating a clock; a sampling circuit, arranged for sampling the signal continuously to generate a plurality of sampled signal; a counter, arranged for counting each sampled signal length corresponding to successive sampled signals each having an identical value; and a determining unit, arranged for identifying a content of the signal according to a plurality of sampled signal lengths.

Abstract: A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected.

Abstract: A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected.

Abstract: Implementing daisy chained ATA host controllers in a single PCI device. The present invention discloses a PCI card that includes a plurality of dominant chips, each of the dominant chips supporting at least one ATA host controller. The PCI card also includes a Flash memory for holding dominant chip settings, an arbiter to control and determine access between the dominant chips and the PCI local bus, and a plurality of ATA connectors corresponding to the ATA host controllers. Each dominant chip includes a byte of memory reserved as a mask to control access to an additional function that may be provided by the dominant chip.

Abstract: Implementing daisy chained ATA host controllers in a single PCI device. The present invention discloses a PCI card that includes a plurality of dominant chips, each of the dominant chips supporting at least one ATA host controller. The PCI card also includes a Flash memory for holding dominant chip settings, an arbiter to control and determine access between the dominant chips and the PCI local bus, and a plurality of ATA connectors corresponding to the ATA host controllers. Each dominant chip includes a byte of memory reserved as a mask to control access to an additional function that may be provided by the dominant chip.