Abstract: An operating method includes: placing a first mask, a second mask, a third mask and a fourth mask on a rotating base, in which each of the first, second, third and fourth masks has a first exposure unit, a second exposure unit, a third exposure unit and a fourth exposure unit; overlaying the first, second, third and fourth masks such that the first exposure unit of the first mask, the second exposure unit of the second mask, the third exposure unit of the third mask and the fourth exposure unit of the fourth mask are arranged adjacently to form an exposure area; simulating a first coordinate information according to the exposure area by an image simulation unit; scanning the exposure area, by a scanning electron microscope (SEM), to obtain a second coordinate information; and comparing the first coordinate information with the second coordinate information.

Abstract: A pattern analysis method includes the steps of: grouping a plurality of polygons in a circuit layout into a plurality of polygon groups; locating a potential defect area of each polygon group according to an aerial image of the circuit layout; determining a representing point of the potential defect area of each polygon group; determining representing points of the plurality of polygons in each polygon group; and comparing a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in one of the polygon groups with a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in another of the polygon groups. The steps aforesaid are executed by a processor in a computer system.

Abstract: A pattern analysis method includes the steps of: grouping a plurality of polygons in a circuit layout into a plurality of polygon groups; locating a potential defect area of each polygon group according to an aerial image of the circuit layout; determining a representing point of the potential defect area of each polygon group; determining representing points of the plurality of polygons in each polygon group; and comparing a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in one of the polygon groups with a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in another of the polygon groups. The steps aforesaid are executed by a processor in a computer system.

Abstract: A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse patterns if d?5a and c?1.5b or if 5a>d?3a and c?1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided.

Abstract: A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.

Abstract: A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.

Abstract: A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse if d?5a and c?1.5b or if 5a>d?3a and c?1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided.

Abstract: A method for matching assistant feature tools includes the steps of: generating an objective assistant feature according to a specific test layout by a first assistant feature tool; generating a compared assistant feature according to the specific test layout by a second assistant feature tool; and determining whether to accept or reject the second assistant feature tool by comparing the compared assistant feature with the objective assistant feature.

Abstract: The present disclosure relates to a replaced photomask including a substrate and a plurality of etched patterns. The plurality of etched patterns are formed on the substrate according to a photomask layout which has a plurality of photomask layout patterns categorized into a plurality of first groups. Each of the first groups includes a plurality of identical initial layout patterns, and each of the first groups is reproduced from an initial layout having a plurality of initial layout patterns categorized into a plurality of second groups to which the plurality of first groups respectively correspond, wherein the plurality of photomask layout patterns respectively correspond to the plurality of initial layout patterns and at least one of the plurality of the photomask layout patterns is replaced by a standardized photomask layout pattern.

Abstract: The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.

Abstract: The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.

Abstract: A phase-shift mask for forming a pattern includes a glass substrate and a pattern, a first phase-shift region, a second phase-shift region and a third phase-shift region on the glass substrate. The first phase-shift region and the second phase-shift region are alternately arranged and the third phase-shift regions are formed at the terminal ends of the first phase-shift region.

Abstract: The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.

Abstract: A phase-shift mask for forming a pattern includes a glass substrate and a pattern, a first phase-shift region, a second phase-shift region and a third phase-shift region on the glass substrate. The first phase-shift region and the second phase-shift region are alternately arranged and the third phase-shift regions are formed at the terminal ends of the first phase-shift region.

Abstract: A photomask with photoresist test patterns and pattern inspection method using four test patterns on the photomask to perform the exposure on the first photoresist layer in order to adjust the photomask. The present invention prevents misalignment of the first photomask. The information associated with the misalignment is provided to the process engineer based on the location of the test patterns.

Abstract: A method for applying T-shaped photo-resist pattern to fabricate a wiring pattern with small structural dimensions. According to the hydroxyl of a chemical-magnified photo-resist layer must participate in a reaction to be able to fabricate the desired exposure pattern, the chemical photo-resist layer is used to form on the semiconductor substrate wafer. By providing an ammonium gas to semiconductor substrate wafers, it causes NH3— to catch the H+ ion of the upper site of the chemical-amplified photo-resist layer. This causes a non-reactive layer over the upper portion when the patterning process for chemical-magnified photo-resist layer is performed, and then to fabricate the T-shaped photo-resist pattern. Furthermore, when the wiring pattern is deposited over the semiconductor substrate wafer, it could be able to form the wiring pattern with small structural dimensions.

Abstract: An overlay mark for monitoring the critical dimension of a non-critical layer, comprising four first bars which are bar-shaped and separated from each other. The four first bars enclose to form a rectangle, and each first bar is correspondingly parallel to each side of the rectangle. The four second bars, wherein each second bar is bar-shaped and separated from each other, and the four second bars are positioned in the rectangle, and each second bar is correspondingly parallel to each side of the rectangle and comprise a plurality of third bars parallel with each other.

Abstract: A photomask with photoresist test patterns and pattern inspection method using four test patterns on the photomask to perform the exposure on the first photoresist layer in order to adjust the photomask. The present invention prevents misalignment of the first photomask. The information associated with the misalignment is provided to the process engineer based on the location of the test patterns.