Abstract: Some implementations described herein include a complementary metal oxide semiconductor image sensor device and techniques to form the complementary metal oxide semiconductor image sensor device. The complementary metal oxide semiconductor image sensor device includes a includes a first array of photodiodes stacked over a second array of photodiodes. A polarization structure is between the first array of photodiodes and the second array of photodiodes. Signaling generated by the first array of photodiodes (e.g., signaling corresponding to unpolarized light waves) may be multiplexed with signaling generated by the second array of photodiodes (e.g., signaling corresponding to polarized light waves). The complementary metal oxide semiconductor image sensor device further includes a filter structure that filters visible light waves and near infrared light waves amongst the first array of photodiodes and the second array of photodiodes.

Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

Abstract: A method and wafer stack that includes a first wafer component, a second wafer component, and third wafer component. The first wafer component includes a frontside and a backside. The wafer stack also includes a second wafer component having a frontside and a backside, such that the frontside of the second wafer component is bonded to the frontside of the first wafer component. In addition, the wafer stack includes a third wafer component having a frontside and a backside, such that the frontside of the third wafer component is bonded to the backside of the second wafer component. The first wafer component includes a composite metal grid array with one or more photodiodes formed on the backside.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Abstract: The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: Some implementations herein provide for a system and methods for in-line monitoring of a sealant being dispensed by a jet nozzle in a beveled region along a perimeter of a stack of semiconductor substrates. The system includes an automated optical inspection system. During the dispensing of the sealant by the jet nozzle, the automated optical inspection system may monitor an amount of an accumulation of the sealant within the beveled region.

Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

Abstract: An integrated circuit includes a first power rail on a back-side of a wafer and being configured to supply a first voltage, a header circuit coupled to the first power rail and being configured to supply the first voltage to the first power rail, a second and third power rail on the back-side of the wafer, a fourth power rail on a front-side of the wafer, and a fifth power rail on the back-side of the wafer. The second and third power rail being configured to supply a second voltage. The fourth power rail includes a first set of conductors configured to supply a third voltage to the header circuit. The fifth power rail is configured to supply the third voltage and is separated from the first power rail in a first and second direction, and is separated from the second and third power rail in the first direction.

Abstract: A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: An IC device includes first and second circuits adjacent each other and over a substrate. The first circuit includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second circuit includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second circuit or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connecting the first IO pattern and a second IO pattern of the second circuit. The second IO pattern is one of the plurality of conductive patterns of the second circuit and is along the first track.

Abstract: Some implementations described herein provide an optoelectronic device and methods of formation. The optoelectronic device is fabricated using a series of operations that includes a patterning operation using a layer of a negative photoresist material, followed by a single dry etch operation, a single wet strip operation, and a single wet etch operation. The series of operations may include a reduced number of operations relative to another series of operations that include a patterning operation using a layer of a positive photoresist material. Through the reduced number of operations, handling-induced damage to the device may be reduced. Additionally, the high absorption structure may include a quantum efficiency that is greater relative to another quantum efficiency of another high absorption structure formed through the series of operations that include the patterning operation using the layer of the positive photoresist material.

Abstract: The invention provides a semiconductor processing machine, which comprises a plurality of chambers, at least one of the chamber is a load-lock chamber, and the load-lock chamber comprises a bottom surface and a top lid opposite to the bottom surface; and a gas pipeline is connected with the top lid of the load-lock chamber.

Abstract: A method for training a cross-domain classifier includes the following steps: (a) obtaining training samples from a first database and test samples from a second database; (b) performing an inference procedure to the test samples by the classifier to generate corresponding predicted labels; (c) for a certain category, obtaining the training samples and the test samples belonging to this category, and training an generative adversarial network (GAN) according to the obtained training samples and test samples; (d) performing a style conversion to the obtained training samples by the GAN to obtain synthetic samples; (e) merging the synthetic samples with the training samples to train the classifier; and repeating the above steps (b) to (e). The classifier will be suitable for cross-domain databases based on this iterative procedure.

Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a first substrate, a second substrate disposed opposite to the first substrate, a first light-shielding strip disposed on the first substrate, a second light-shielding strip disposed between the first substrate and the second substrate and color filter patterns disposed on the second light-shielding strip. An overlapping region is the first light-shielding strip overlapping the second light-shielding strip and has a total thickness, a first non-overlapping region of the first light-shielding strip and a second non-overlapping region of the second light-shielding strip are outside the overlapping region, the second light-shielding strip in the second non-overlapping region has a thickness different from the total thickness. In a cross-section view, a part of the color filter patterns includes a convex portion corresponding to the first or the second light-shielding strip.

Abstract: A multifunctional physical store system with automatic sterilization and disinfection functions includes a central process device, and a disinfection device, an order device, a sterilization device, and a serve device that are coupled with the central process device. The system is applied to a physical store. The disinfection device is applied for carrying out the disinfection operation on the environment of the physical store. The sterilization device is applied for carryout surface sterilization on the people entering the store. The order device and the serve device are applied for people to order and acquire meals. Therefore, the application of various devices facilitates a nearly dust-free and sterile environment in the store, lowering the possibility of virus or bacterial infection between people in the operation area and the customers.

Abstract: Provided are a lens composition that filters out and reduces transmittance of blue light and a lens formed of the composition. The lens composition includes: 40-50% thermoplastic material, 34-46% plasticizer, 2.6-4.4% quinophthalone, 2.1-3.6% perynone, 1.3-2.3% anthraquinone, and 0.48-0.82% luminophor. The lens is formed by having the composition mixed and subjected to pressing or injection molding so that the lens reduces the transmittance of blue light in the wavelength range of 380-550 nm to about 35-65% thereby reducing the harm caused thereby to human eyes.

Abstract: An interface card includes a circuit board having an interface unit, a communication operation processing unit mounted on the circuit board, a SIM card slot mounted on the circuit board, and a M2M SIM mounted on the circuit board. The interface unit is coupled with an interface card slot of an external electronic equipment. The SIM card slot outputs at least one signal to the communication operation processing unit. The M2M SIM is provided with a communication protocol of a predetermined telecommunication operator and outputs at least one signal to the communication operation processing unit. Thus, the interface card has a SIM card slot and a M2M SIM to provide two wireless communication connection modes for selection of a user, so that the user can select any one of the wireless communication connection modes according the practical requirement.