Patents by Inventor Kuo-Liang Deng

Kuo-Liang Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9204581
    Abstract: A method for performing chip level electromagnetic interference (EMI) reduction is provided, where the method is applied to an electronic device. The method includes: providing at least one EMI suppression circuit within at least one chip of the electronic device; and utilizing the at least one EMI suppression circuit within the at least one chip to perform EMI reduction on at least one signal within the at least one chip. In particular, the at least one chip includes a first chip and a second chip; and the at least one EMI suppression circuit includes a first EMI suppression circuit positioned within the first chip, and further includes a second EMI suppression circuit positioned within the second chip. An associated apparatus is also provided.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: December 1, 2015
    Assignee: MEDIATEK INC.
    Inventors: Long-Kun Yu, Kuo-Liang Deng
  • Patent number: 8648779
    Abstract: A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Lung Hsueh, Yung-Chow Peng, Kuo-Liang Deng
  • Patent number: 8115514
    Abstract: An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second pre-charge transistor has a source-drain path coupled between the positive power supply node and the second output node. The integrated circuit structure further includes a delay-inverter coupled between a signal input node and inputs of a first NMOS transistor and a second NMOS transistor in the latch. The delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Kuo-Liang Deng
  • Publication number: 20110090198
    Abstract: A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 21, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Lung HSUEH, Yung-Chow PENG, Kuo-Liang DENG
  • Patent number: 7894173
    Abstract: An integrated circuit device includes a first pad and a second pad; electrostatic discharging (ESD) devices coupling the first pad and the second pad to a discharging path; a transformer including a first end, a second end, a third end and a fourth end, wherein the first end and the second end are coupled to the first pad and the second pad, respectively; and a transceiver circuit coupled to the first end and the second end of the transformer.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Liang Deng, Tsung-Yang Hung
  • Publication number: 20100301900
    Abstract: An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second pre-charge transistor has a source-drain path coupled between the positive power supply node and the second output node. The integrated circuit structure further includes a delay-inverter coupled between a signal input node and inputs of a first NMOS transistor and a second NMOS transistor in the latch. The delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor.
    Type: Application
    Filed: March 30, 2010
    Publication date: December 2, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Liang Deng
  • Publication number: 20100067154
    Abstract: An integrated circuit device includes a first pad and a second pad; electrostatic discharging (ESD) devices coupling the first pad and the second pad to a discharging path; a transformer including a first end, a second end, a third end and a fourth end, wherein the first end and the second end are coupled to the first pad and the second pad, respectively; and a transceiver circuit coupled to the first end and the second end of the transformer.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 18, 2010
    Inventors: Kuo-Liang Deng, Tsung-Yang Hung