Patents by Inventor Kuo-Lun Huang

Kuo-Lun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133698
    Abstract: A method of route planning and an electronic device using the same method are provided. The method includes: obtaining multiple route points, and generating a route set according to the route points, wherein a first route in the route set includes a first order corresponding to the route points, wherein the first order includes a first route point and a second route point adjacent to the first route point; obtaining multiple weights respectively corresponding to the route points; calculating a first score of the first route according to a distance or time between the first route point and the second route point and the weights, and selecting the first route from the route set as a recommended route according to the first score; and outputting the recommended route.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 25, 2024
    Applicant: Wistron Corporation
    Inventor: Kuo-Lun Huang
  • Patent number: 11961840
    Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240120402
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
  • Patent number: 11948987
    Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240013406
    Abstract: A trajectory predicting method and a computing system for trajectory prediction are provided. In the method, feature extraction is respectively performed on past trajectories of multiple target objects through an encoder to generate first trajectory information of the target objects. A pooling process is performed on the first trajectory information of the target objects to generate second trajectory information of the target objects. The second trajectory information of each target object includes location relationships relative to other target objects. Third trajectory information is obtained from the past trajectories of the target objects. The third trajectory information includes a moving direction, scene information, and/or a moving mode. The predicted trajectories of the target objects are generated according to the second trajectory information and the third trajectory information through a decoder. Accordingly, the accuracy of prediction can be improved.
    Type: Application
    Filed: October 27, 2022
    Publication date: January 11, 2024
    Applicant: Wistron Corporation
    Inventors: Xiu Zhi Chen, Jyun Hong He, Yen Lin Chen, Yung Jen Chen, Yi Kai Chiu, You Shiuan Lin, Kuo-Lun Huang, Ke Kang Chen, Shao-Chi Chen
  • Patent number: 11824444
    Abstract: A driver chip for a half-bridge circuit includes a drive module and a programming module. The drive module is configured to receive an enabling signal and at least one input signal. The drive module outputs a high-side output signal to a high-side switch and a low-side output signal to a low-side switch, respectively. The programming module includes a decoding unit configured to receive the enabling signal and the at least one input signal. The programming module further includes a preset unit coupled to the decoding unit. The decoding unit outputs decoded data to the preset unit, and the preset unit outputs a circuit parameter.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: November 21, 2023
    Assignee: MOTOR SEMICONDUCTOR CO., LTD.
    Inventor: Kuo-Lun Huang
  • Patent number: 11776292
    Abstract: An object identification method includes: generating a tracking sample and an adversarial sample; training a teacher model according to the tracking sample; and initializing a student model according to the teacher model. The student model adjusts a plurality of parameters according to the teacher model and the adversarial sample, in response to the vector difference between the output result of the student model and the output result of the teacher model being lower than the learning threshold, the student model is deemed to have completed training, and the student model is extracted as an object identification model.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 3, 2023
    Assignee: WISTRON CORP
    Inventor: Kuo-Lun Huang
  • Publication number: 20230207386
    Abstract: A method of increasing the resistivity of a silicon carbide wafer includes providing a silicon carbide wafer with a first resistivity, and applying a microwave to treat the silicon carbide wafer. The treated silicon carbide wafer has a second resistivity. The second resistivity is higher than the first resistivity. The microwave treated silicon carbide wafer can be applied in a high-frequency device.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 29, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mao-Nan CHANG, Ta-Ching HSIAO, Kuo-Lun HUANG, Pei-Ying CHEN
  • Publication number: 20230187394
    Abstract: A half-bridge circuit package structure includes a chip pad, a first metal island, a driving chip, an upper bridge switch, and a lower bridge switch. The driving chip includes a ground pad and a high side ground pad. The upper bridge switch includes a first enhancement mode transistor and a first depletion mode transistor. A drain pad of the first depletion mode transistor is electrically connected to the first metal island. The lower bridge switch includes a second enhancement mode transistor and a second depletion mode transistor. A source pad of the second depletion mode transistor is electrically connected to a drain pad of the second enhancement mode transistor. A drain pad of the second depletion mode transistor is electrically connected to the first metal island.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventor: Kuo-Lun HUANG
  • Patent number: 11609616
    Abstract: A portable electronic apparatus including a first body, a second body, and a keyboard is provided. The second body is pivotally connected to the first body. The keyboard is disposed on the first body and includes a plurality of key structures. One of the key structures includes an elevating platform, a key cap, and a camera. The key cap is detachably mounted to the elevating platform, and the camera is mounted at one side of the key cap facing the elevating platform. After the camera is detached from the elevating platform together with the key cap, the camera is mounted and positioned to the second body together with the key cap, and at least a portion of the camera is exposed to the outside.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 21, 2023
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Kuo-Lun Huang
  • Patent number: 11541351
    Abstract: A method for removing boron is provided, which includes (a) mixing a carbon source material and a silicon source material in a chamber to form a solid state mixture, (b) heating the solid state mixture to a temperature of 1000° C. to 1600° C., and adjusting the pressure of the chamber to 1 torr to 100 torr. The method also includes (c) conducting a gas mixture of a first carrier gas and water vapor into the chamber to remove boron from the solid state mixture, and (d) conducting a second carrier gas into the chamber.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 3, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching Hsiao, Chu-Pi Jeng, Kuo-Lun Huang, Mu-Hsi Sung, Keng-Yang Chen, Li-Duan Tsai
  • Publication number: 20220261047
    Abstract: A portable electronic apparatus including a first body, a second body, and a keyboard is provided. The second body is pivotally connected to the first body. The keyboard is disposed on the first body and includes a plurality of key structures. One of the key structures includes an elevating platform, a key cap, and a camera. The key cap is detachably mounted to the elevating platform, and the camera is mounted at one side of the key cap facing the elevating platform. After the camera is detached from the elevating platform together with the key cap, the camera is mounted and positioned to the second body together with the key cap, and at least a portion of the camera is exposed to the outside.
    Type: Application
    Filed: September 15, 2021
    Publication date: August 18, 2022
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Kuo-Lun Huang
  • Publication number: 20220198181
    Abstract: An object identification method includes: generating a tracking sample and an adversarial sample; training a teacher model according to the tracking sample; and initializing a student model according to the teacher model. The student model adjusts a plurality of parameters according to the teacher model and the adversarial sample, in response to the vector difference between the output result of the student model and the output result of the teacher model being lower than the learning threshold, the student model is deemed to have completed training, and the student model is extracted as an object identification model.
    Type: Application
    Filed: March 15, 2021
    Publication date: June 23, 2022
    Inventor: Kuo-Lun Huang
  • Patent number: 11309298
    Abstract: A light-emitting diode device with a driving mechanism is provided. A first light-emitting diode chip, a second light-emitting diode chip and a third light-emitting diode chip are arranged on a driver circuit chip, and respectively configured to emit red light, green light and blue light. A first contact of the light-emitting diode chip, a first contact of the second light-emitting diode chip and a first contact of the third light-emitting diode chip are respectively in direct electrical contact with a first output contact, a second output contact and a third output contact of the driver circuit chip in a flip-chip manner. A second contact of the first light-emitting diode chip, a second contact of the second light-emitting diode chip and a second contact of the third light-emitting diode chip are in direct electrical contact with a common contact of the driver circuit chip.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: April 19, 2022
    Assignee: MY-SEMI INC.
    Inventors: Cheng-Han Hsieh, Kuo-Lun Huang, Chun-Ting Kuo
  • Patent number: 11302806
    Abstract: The present invention discloses a double-gate trench-type insulated-gate bipolar transistor device. A first trench and a second trench, which are located in a P-type doped well layer, and separate from each other, are extended into a lightly-doped N-type drift layer. A heavily-doped P-type source region and a heavily-doped N-type source region, which are sequentially connected, are located between the first trench and the second trench, and are arranged at an upper part of the P-type doped well layer in a horizontal direction. The heavily-doped P-type source region is located at a periphery of the second trench, a middle part and the upper part of the P-type doped well layer are provided with an N-type doped well layer and a P-type doped base region layer, respectively. The heavily-doped P-type source region and the heavily-doped N-type source region are both located at an upper part of the P-type doped base region layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: April 12, 2022
    Assignee: HUGE POWER LIMITED TAIWAN BRANCH (B.V.I.)
    Inventors: Jia-Ming Kuo, Chung-Wei Yu, Kuo-Lun Huang, Chao-Tsung Chang
  • Publication number: 20210275965
    Abstract: A method for removing boron is provided, which includes (a) mixing a carbon source material and a silicon source material in a chamber to form a solid state mixture, (b) heating the solid state mixture to a temperature of 1000° C. to 1600° C., and adjusting the pressure of the chamber to 1 torr to 100 torr. The method also includes (c) conducting a gas mixture of a first carrier gas and water vapor into the chamber to remove boron from the solid state mixture, and (d) conducting a second carrier gas into the chamber.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching HSIAO, Chu-Pi JENG, Kuo-Lun HUANG, Mu-Hsi SUNG, Keng-Yang CHEN, Li-Duan TSAI
  • Patent number: 11052348
    Abstract: A method for removing boron is provided, which includes (a) mixing a carbon source material and a silicon source material in a chamber to form a solid state mixture, (b) heating the solid state mixture to a temperature of 1000° C. to 1600° C., and adjusting the pressure of the chamber to 1 torr to 100 torr. The method also includes (c) conducting a gas mixture of a first carrier gas and water vapor into the chamber to remove boron from the solid state mixture, and (d) conducting a second carrier gas into the chamber.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: July 6, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching Hsiao, Chu-Pi Jeng, Kuo-Lun Huang, Mu-Hsi Sung, Keng-Yang Chen, Li-Duan Tsai
  • Patent number: 11046582
    Abstract: A method of purifying silicon carbide powder includes: providing a container with a surface coated by a nitrogen-removal metal layer, wherein the nitrogen-removal metal layer is tantalum, niobium, tungsten, or a combination thereof; putting a silicon carbide powder into the container to contact the nitrogen-removal metal layer; and heating the silicon carbide powder under an inert gas at a pressure of 400 torr to 760 torr at 1700° C. to 2300° C. for 2 to 10 hours, thereby reducing the nitrogen content of the silicon carbide powder.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 29, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching Hsiao, Chu-Pi Jeng, Mu-Hsi Sung, Kuo-Lun Huang
  • Publication number: 20210139330
    Abstract: A method of purifying silicon carbide powder includes: providing a container with a surface coated by a nitrogen-removal metal layer, wherein the nitrogen-removal metal layer is tantalum, niobium, tungsten, or a combination thereof; putting a silicon carbide powder into the container to contact the nitrogen-removal metal layer; and heating the silicon carbide powder under an inert gas at a pressure of 400 torr to 760 torr at 1700° C. to 2300° C. for 2 to 10 hours, thereby reducing the nitrogen content of the silicon carbide powder.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 13, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching HSIAO, Chu-Pi JENG, Mu-Hsi SUNG, Kuo-Lun HUANG
  • Patent number: 10944152
    Abstract: An antenna structure includes a metal frame. The metal frame includes a first gap, a second gap, a third gap, and a fourth gap to separate a first antenna, a second antenna, a third antenna, and a fourth antenna from the metal frame. The metal frame includes a fifth antenna. The first antenna, the second antenna, the third antenna, and the fourth antenna cooperatively form a first multiple-input multiple-output (MIMO) antenna to provide a 4×4 multiple-input multiple-output function in a second frequency band. The first antenna, the second antenna, the third antenna, and the fifth antenna cooperatively form a second MIMO antenna to provide a 4×4 multiple-input multiple-output function in a third frequency band. The first antenna and the third antenna cooperatively form a third MIMO antenna to provide a 2×2 multiple-input multiple-output function in a first frequency band.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 9, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Jia-Hung Hsiao, Shu-Wei Jhang, Wen-Yuan Chen, Chang-Hsin Ou, Ming-Yu Chou, Chia-Ming Liang, Kuo-Lun Huang