Patents by Inventor Kuo Lung Lei

Kuo Lung Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262758
    Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 7008867
    Abstract: A method for forming a copper bump for flip chip bonding having improved oxidation resistance and thermal stability including providing a copper column having a thickness of at least about 40 microns overlying a metallurgy including an uppermost copper metal layer and a lowermost titanium layer the lowermost titanium layer in contact with an exposed copper bonding pad portion surrounded by a passivation layer; and, selectively depositing at least one protective metal layer over the copper column according to an electrolytic deposition process.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: March 7, 2006
    Assignee: Aptos Corporation
    Inventor: Kuo Lung Lei
  • Publication number: 20040256719
    Abstract: A wafer level, chip scale package suitable for a MEMS type device employs a solder bead between a protective cap and the chip substrate to hermetically seal active areas of the chip. Solder is electroplated onto a metallized layer on the cap through a photoresist mask that is subsequently removed to leave a solder bead patterned to completely surround the active chip areas. The cap is mounted on the chip substrate using a spacer to hold the cap and the substrate in spaced relationship while the cap is welded to the chip substrate using the solder bead. The spacer is subsequently removed, preferably during dicing of a wafer on which the chips are formed.
    Type: Application
    Filed: June 18, 2003
    Publication date: December 23, 2004
    Applicant: Aptos Corporation
    Inventor: Kuo Lung Lei
  • Publication number: 20040166661
    Abstract: A method for forming a copper bump for flip chip bonding having improved oxidation resistance and thermal stability including providing a copper column having a thickness of at least about 40 microns overlying a metallurgy including an uppermost copper metal layer and a lowermost titanium layer the lowermost titanium layer in contact with an exposed copper bonding pad portion surrounded by a passivation layer; and, selectively depositing at least one protective metal layer over the copper column according to an electrolytic deposition process.
    Type: Application
    Filed: February 21, 2003
    Publication date: August 26, 2004
    Applicant: Aptos Corporation
    Inventor: Kuo Lung Lei
  • Publication number: 20040166662
    Abstract: A method of forming a wafer level chip scale package including forming a trench through the semiconductor wafer at a location between two adjacent to chip portions and forming a backside under bump metallurgy connection to an under bump metallurgy on the front face of the semiconductor wafer for each chip portion.
    Type: Application
    Filed: February 21, 2003
    Publication date: August 26, 2004
    Applicant: Aptos Corporation
    Inventor: Kuo-Lung Lei
  • Patent number: 6100107
    Abstract: A preparation method for an integrated assembly of a microchannel and an element is disclosed. In the preparation method of this invention, an element is prepared between a substrate and a sacrificial layer. Two protection layers, which are resistant to etchant for said substrate and said sacrificial layer, are prepared to isolate said element from its ambient environment. Said sacrificial layer defines an area to be etched off such that a microchannel may be formed. A coating layer with etching windows is then prepared on said sacrificial layer and the assembly is etched in an etchant to etch off said sacrificial layer and an area of said substrate beneath said sacrificial layer. An integrated assembly of a closed microchannel and an element is then accomplished. In the invented method, no bonding process is necessary and the integrated assembly so prepared has a planarization surface. This invention also disclosed a microchannel-element assembly prepared under the method of this invention.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: August 8, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Lung Lei, Ten-Hsing Jaw, Chen-Kuei Chung, Dong-Sing Wuu, Ching-Yi Wu