Patents by Inventor Kuo Lung Pan
Kuo Lung Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200211922Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.Type: ApplicationFiled: August 1, 2019Publication date: July 2, 2020Inventors: Shu-Rong Chun, Kuo Lung Pan, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
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Publication number: 20200212018Abstract: A packaged semiconductor device including an integrated passive device-containing package component disposed between a power module and an integrated circuit-containing package and a method of forming the same are disclosed. In an embodiment, a device includes a first package component including a first integrated circuit die; a first encapsulant at least partially surrounding the first integrated circuit die; and a redistribution structure on the first encapsulant and coupled to the first integrated circuit die; a second package component bonded to the first package component, the second package component including an integrated passive device; and a second encapsulant at least partially surrounding the integrated passive device; and a power module attached to the first package component through the second package component.Type: ApplicationFiled: October 1, 2019Publication date: July 2, 2020Inventors: Chi-Hui Lai, Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 10658258Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.Type: GrantFiled: February 21, 2019Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Lung Pan, Hao-Yi Tsai, Tin-Hao Kuo
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Publication number: 20200091114Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo Lung Pan, Tin-Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
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Publication number: 20200075562Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.Type: ApplicationFiled: August 2, 2019Publication date: March 5, 2020Inventors: Chen-Hua Yu, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Hsiu-Jen Lin, Hao-Jan Pei, Ching-Hua Hsieh
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Publication number: 20200006220Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.Type: ApplicationFiled: February 4, 2019Publication date: January 2, 2020Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 10461023Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.Type: GrantFiled: January 30, 2018Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Yen Chang, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Tzung-Hui Lee, Teng-Yuan Lo, Hao-Chun Ting
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Publication number: 20190312018Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.Type: ApplicationFiled: September 11, 2018Publication date: October 10, 2019Inventors: Yu-Chia Lai, Kuo Lung Pan, Hung-Yi Kuo, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20190131223Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.Type: ApplicationFiled: January 30, 2018Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Yen Chang, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Tzung-Hui Lee, Teng-Yuan Lo, Hao-Chun Ting
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Publication number: 20190123021Abstract: A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.Type: ApplicationFiled: December 10, 2018Publication date: April 25, 2019Inventors: Kuo Lung Pan, Wei Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
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Patent number: 10153249Abstract: A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.Type: GrantFiled: April 7, 2017Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Lung Pan, Wei Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
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Patent number: 10134706Abstract: Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.Type: GrantFiled: August 14, 2017Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Lung Pan, Ching-Wen Hsiao, Chen-Shien Chen
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Patent number: 10125014Abstract: Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.Type: GrantFiled: December 15, 2017Date of Patent: November 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Lung Pan, Chung-Shi Liu, Hao-Yi Tsai, Yu-Feng Chen, Yu-Jen Cheng
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Publication number: 20180233382Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shing-Chao CHEN, Chih-Wei LIN, Meng-Tse CHEN, Hui-Min HUANG, Ming-Da CHENG, Kuo-Lung PAN, Wei-Sen CHANG, Tin-Hao KUO, Hao-Yi TSAI
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Publication number: 20180111827Abstract: Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.Type: ApplicationFiled: December 15, 2017Publication date: April 26, 2018Inventors: Kuo Lung Pan, Chung-Shi Liu, Hao-Yi Tsai, Yu-Feng Chen, Yu-Jen Cheng
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Patent number: 9947552Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.Type: GrantFiled: June 28, 2016Date of Patent: April 17, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 9935081Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a substrate, and adhering a first semiconductor device. Chip stacks are formed by providing a plurality of semiconductor devices and bonding them to the substrate and the first semiconductor device. At least one of the provided semiconductor devices is physically connected to both the substrate and the first semiconductor device it is stack on. Other semiconductor devices may stacked by forming conductive channels in the first semiconductor device, and placing the other semiconductor devices in physical contact with the first semiconductor device and the conductive channels.Type: GrantFiled: August 20, 2014Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Lung Pan, Yu-Feng Chen, Chen-Shien Chen, Mirng-Ji Lii
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Patent number: 9850126Abstract: Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.Type: GrantFiled: December 31, 2015Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Lung Pan, Chung-Shi Liu, Hao-Yi Tsai, Yu-Feng Chen, Yu-Jen Cheng
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Patent number: 9837346Abstract: An example method includes providing a packaging device includes a substrate having an integrated circuit die mounting region. A plurality of microstructures, each including an outer insulating layer over a conductive material, are disposed proximate a side of the integrated circuit die mounting region. An underfill material is disposed between the substrate and the integrated circuit die, the microstructures preventing spread of the underfill. In another example method, a via can be formed in a substrate and the substrate etched to form a bump or pillar from the via. An insulating material can be formed over the bump or pillar. In another example method, a photoresist deposited over a seed layer and patterned to form openings. A conductive material is plated in the openings, forming a plurality of pillars or bumps. The photoresist and exposed seed layer are removed. The conductive material is oxidized to form an insulating material.Type: GrantFiled: March 15, 2017Date of Patent: December 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo Lung Pan, Yu-Feng Chen, Chen-Shien Chen
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Publication number: 20170345788Abstract: Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.Type: ApplicationFiled: August 14, 2017Publication date: November 30, 2017Inventors: Kuo Lung Pan, Ching-Wen Hsiao, Chen-Shien Chen