Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

Abstract: A method for making a silk protein film includes providing an aqueous solution of a silk protein, and annealing a mixture including the aqueous solution of the silk protein and a water-soluble polyhydroxy compound that is present in an amount ranging from 20 wt % to 60 wt % based on a total amount of the silk protein and the water-soluble polyhydroxy compound at an annealing temperature that is higher than 50° C. and lower than 180° C. and under a relative humidity of not higher than 30%, so as to form the silk protein film.

Abstract: A method of manufacturing decoration foils and a release layer and an adhesive layer of the decoration foil, and decoration foils manufactured by the same are revealed. First take waste containing polyethylene terephthalate (PET) to react with an alcohol and get a first product. Then the first product is allowed to react with a compound containing isocyanate group and polyol to obtain polyurethane (PU) material. The PU material obtained is used for manufacturing at least one of a release layer and an adhesive of decoration foils to get the decoration foil.

Abstract: A method for making a silk protein film includes providing an aqueous solution of a silk protein, and annealing a mixture including the aqueous solution of the silk protein and a water-soluble polyhydroxy compound that is present in an amount ranging from 20 wt % to 60 wt % based on a total amount of the silk protein and the water-soluble polyhydroxy compound at an annealing temperature that is higher than 50° C. and lower than 180° C. and under a relative humidity of not higher than 30%, so as to form the silk protein film.

Abstract: An ultraviolet (UV) and infrared (IR) blocking coating and a method for preparing the same are revealed. The coating provides functions of UV blocking and IR blocking by addition of nanoparticles that blocks UV rays and IR rays, or by other additives with the same functions such as organic/inorganic compounds or dyes.

Abstract: This invention relates to a method for making high metallic luster, high impedance on flexible polymer based material, in which a lustrous layer is coated on the first surface of a flexible polymer based material by means of wet coating and a color protection layer is further coated on the lustrous layer or the second surface of the flexible polymer based material. In this manner, metal-like feeling and luster is enhanced by the lustrous layer such that the flexible polymer based material has low metal shielding effect or light-shield capability. In addition, the transmittance of light and electromagnetic wave in demanded range become better so that the interference on the quality of transmission and receiving can be avoided.

Abstract: A mist humidifier has a lower space receiving a main water tank for storing water and an upper space divided into an evaporative cavity and a blower cavity. The evaporative cavity is divided into a first water chamber for storing water fed from main water tank having a float ball safety valve, a second water chamber for receiving a nebulizer for vaporizing water for creating cool mist, a third water chamber for receiving a heater for heating water for creating a hot mist, and a water supply tube provided on the bottom of the first water chamber in fluid communication with the second and third water chambers so as to keep all water chambers at a constant equal level, whereby a mist having a temperature at a constant level is discharged into the environment when the humidifier is activated.

Abstract: A combination writing instrument comprising a plurality of nib devices detachably mounted at the front of pen holder, all of the nib devices being mounted in a head-to-tail connection with a uniform ink flow system to induce a constant and uniform ink flow from an ink reservoir to the front-most writing point for immediate and smooth writing, so that the user can select one of the nib devices to perform a desired writing purpose and enjoy a variety of writing modes.