Patents by Inventor Kuo-Ming Wu

Kuo-Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12293946
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Lung Lin, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Hau-Yi Hsiao
  • Patent number: 12289905
    Abstract: A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: April 29, 2025
    Assignee: Parabellum Strategic Opportunities Fund LLC
    Inventors: Jia-Rui Lee, Kuo-Ming Wu, Yi-Chun Lin
  • Patent number: 12278151
    Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Hau-Yi Hsiao, Guanyu Luo, Ping-Tzu Chen, Cheng-Yuan Tsai
  • Publication number: 20250118710
    Abstract: A semiconductor device is formed by bonding a first semiconductor die and a second semiconductor die at bonding pads in the first semiconductor die with bonding vias in the second semiconductor die, and by bonding dielectric layers in the first semiconductor die and in the second semiconductor die. Omitting bonding pads from the second semiconductor device, and instead using the bonding vias to bond the first and second semiconductor dies, provides a greater amount of spacing between the bonding vias of the second semiconductor die in that the bonding vias have lesser widths than bonding pads. This enables a greater amount of dielectric material of the dielectric layers of the second semiconductor device to be placed between the bonding vias without (or with minimally) increasing the lateral size of the second semiconductor die.
    Type: Application
    Filed: March 26, 2024
    Publication date: April 10, 2025
    Inventors: Kuo-Ming WU, Ru-Liang LEE, Sheng-Chau CHEN
  • Publication number: 20250105056
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Patent number: 12211741
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Patent number: 12205855
    Abstract: The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hau-Yi Hsiao, Kuo-Ming Wu, Chun Liang Chen, Sheng-Chau Chen
  • Publication number: 20240379468
    Abstract: The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Hau-Yi Hsiao, Kuo-Ming Wu, Chun Liang Chen, Sheng-Chau Chen
  • Publication number: 20240379462
    Abstract: In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Hong-Shyang Wu, Kuo-Ming Wu
  • Publication number: 20240379716
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Sin-Yao Huang, Hung-Ling Shih, Kuo-Ming Wu, Hung-Wen Hsu
  • Publication number: 20240371666
    Abstract: Some implementations herein provide for a system and methods for in-line monitoring of a sealant being dispensed by a jet nozzle in a beveled region along a perimeter of a stack of semiconductor substrates. The system includes an automated optical inspection system. During the dispensing of the sealant by the jet nozzle, the automated optical inspection system may monitor an amount of an accumulation of the sealant within the beveled region.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 7, 2024
    Inventors: Hau-Yi HSIAO, Kuo-Ming WU, Sheng-Chau CHEN, Ru-Liang LEE
  • Publication number: 20240363469
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure has a plurality of interconnects disposed within a dielectric structure. A dielectric material is along a sidewall of the interconnect structure. The dielectric material extends to within cracks in the sidewall of the dielectric structure.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Publication number: 20240363680
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Yang CHEN, Tian Sheng LIN, Yi-Cheng CHIU, Hung-Chou LIN, Yi-Min CHEN, Kuo-Ming WU, Chiu-Hua CHUNG
  • Publication number: 20240363613
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Cheng-Hsien CHOU, Sheng-Chau CHEN, Cheng-Yuan TSAI
  • Publication number: 20240355784
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 12125763
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Publication number: 20240339422
    Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.
    Type: Application
    Filed: April 10, 2023
    Publication date: October 10, 2024
    Inventors: Che Wei YANG, Kuo-Ming WU, Sheng-Chau CHEN, Cheng-Yuan TSAI, Hau-Yi HSIAO, Chung-Yi YU
  • Publication number: 20240332065
    Abstract: The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Inventors: Yao-Hong You, Dah-Chuen Ho, Kuo-Ming Wu, Ying-De Chen, Yi-Min Chen
  • Publication number: 20240316724
    Abstract: Some implementations herein describe a chemical-mechanical planarization tool including a polishing pad. The chemical-mechanical planarization tool including the polishing pad may perform a polishing operation to a semiconductor substrate. The polishing operation may generate, along a perimeter of the semiconductor substrate, a roll-off profile that satisfies a threshold. The polishing pad includes two or more regions, where each region includes a different pad surface pattern. Each region including a different pad surface pattern may correspond to a different polishing rate. Techniques using the polishing pad having such zone and pad surface pattern combinations allow for a focused and a controlled polishing of the semiconductor substrate, including along the perimeter of the semiconductor substrate to tightly control the roll-off profile.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 26, 2024
    Inventors: Hau-Yi HSIAO, Kuo-Ming WU, Sheng-Chau CHEN
  • Patent number: 12087756
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Ming Wu, Ming-Che Lee, Hau-Yi Hsiao, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai