Abstract: A Schottky diode includes an n-type region, an anode disposed on the n-type region, a buried p-type region, and a shallow p-type region. An interface between the anode and the n-type region forms a Schottky barrier. An n-type channel portion of the n-type region is disposed between the buried p-type region and the shallow p-type region. The anode may also contact the annular shallow p-type region. In an annular configuration, the buried p-type region and the shallow p-type region are annular regions, and the n-type region includes a central portion encircled by the annular shallow p-type region and an annular peripheral portion of the n-type region which encircles the annular shallow p-type region. In one application, a buck converter includes the Schottky diode.

Abstract: The present disclosure, in some embodiments, relates to method. The method includes bonding a second wafer to a first wafer to form a multi-dimensional integrated chip structure. A first edge trimming cut is performed at a first lateral distance from a central region of the multi-dimensional integrated chip structure. A second edge trimming cut is performed at a second lateral distance from the central region of the multi-dimensional integrated chip structure. The second lateral distance is larger than the first lateral distance.

Abstract: A gate-all-around (GAA) high voltage transistor of the laterally double-diffused metal-oxide semiconductor (LDMOS) type has a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by a first source/drain region, a body region, and a diffusion region. The first source/drain region is on top, the body region is in the middle, and the diffusion region is underneath. A loop-shaped shallow trench isolation (STI) region surrounds the loop-shaped gate electrode. The diffusion region begins inside the loop-shaped gate electrode, extends under the loop-shaped gate electrode and the loop-shaped STI region, and rises outside the loop-shaped STI region to join with a second source/drain region. This structure allows pitch to be reduced by 40% or linear drive current to be doubled in comparison to an asymmetric NMOS transistor providing otherwise equivalent functionality.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region and a gate structure extending into the substrate, wherein a portion of the gate structure below a top surface of the substrate abuts the isolation region. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Abstract: A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: A semiconductor device is formed by bonding a first semiconductor die and a second semiconductor die at bonding pads in the first semiconductor die with bonding vias in the second semiconductor die, and by bonding dielectric layers in the first semiconductor die and in the second semiconductor die. Omitting bonding pads from the second semiconductor device, and instead using the bonding vias to bond the first and second semiconductor dies, provides a greater amount of spacing between the bonding vias of the second semiconductor die in that the bonding vias have lesser widths than bonding pads. This enables a greater amount of dielectric material of the dielectric layers of the second semiconductor device to be placed between the bonding vias without (or with minimally) increasing the lateral size of the second semiconductor die.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.

Abstract: The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.

Abstract: In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.

Abstract: Some implementations herein provide for a system and methods for in-line monitoring of a sealant being dispensed by a jet nozzle in a beveled region along a perimeter of a stack of semiconductor substrates. The system includes an automated optical inspection system. During the dispensing of the sealant by the jet nozzle, the automated optical inspection system may monitor an amount of an accumulation of the sealant within the beveled region.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure has a plurality of interconnects disposed within a dielectric structure. A dielectric material is along a sidewall of the interconnect structure. The dielectric material extends to within cracks in the sidewall of the dielectric structure.

Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.