Abstract: A calibration circuit and calibration method for a successive approximation register analog-to-digital converter (SAR ADC) are disclosed. The SAR ADC includes a comparator and generates a digital code. The calibration method includes the following steps: (a) creating a voltage difference between two inputs of the comparator, with the absolute value of the voltage difference being smaller than or equal to the absolute value of the voltage corresponding to the least significant bit (LSB) of the digital code; (b) updating a count value according to whether a timer of the SAR ADC issues a time-out signal, the timer issuing the time-out signal after a delay time has elapsed; (c) repeating steps (a) through (b) a predetermined number of times; (d) calculating a probability based on the predetermined number of times and the count value; and (e) adjusting the delay time according to the probability.

Abstract: A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

Abstract: A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub-ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

Abstract: A charge-redistribution successive approximation ADC includes: a comparator, generating a comparison result; a register, storing a digital output code, determining a bit value of the digital output code according to the comparison value; a control unit, generating a control signal according to the digital output code; a plurality of first capacitors, each including a first end and a second end, the first end coupled to a first input end of the comparator; at least one second capacitor, including a third end and a fourth end, the third end coupled to the first input end of the comparator. Before the voltages of the second end of each first capacitor and the fourth end of the second capacitor are switched, the second end is coupled to a first voltage and the fourth end is coupled to a second voltage different from the first voltage.

Abstract: A charge-redistribution successive approximation ADC includes: a comparator, generating a comparison result; a register, storing a digital output code, determining a bit value of the digital output code according to the comparison value; a control unit, generating a control signal according to the digital output code; a plurality of first capacitors, each including a first end and a second end, the first end coupled to a first input end of the comparator; at least one second capacitor, including a third end and a fourth end, the third end coupled to the first input end of the comparator. Before the voltages of the second end of each first capacitor and the fourth end of the second capacitor are switched, the second end is coupled to a first voltage and the fourth end is coupled to a second voltage different from the first voltage.

Abstract: The present invention relates to a method and a circuit for power switching. The method comprises the steps of: providing a operation circuit; receiving a command from a Host and setting up a power mode of the operation circuit; supplying a first rated consuming power source and then a second rated consuming power source to the operation circuit via the power switching circuit according to power mode; detecting the transferring process form the first rated consuming power source to second rated consuming power source; and preventing over current according to detecting result.

Abstract: The present invention relates to a method and a circuit for power switching. The method comprises the steps of: providing a operation circuit; receiving a command from a Host and setting up a power mode of the operation circuit; supplying a first rated consuming power source and then a second rated consuming power source to the operation circuit via the power switching circuit according to power mode; detecting the transferring process form the first rated consuming power source to second rated consuming power source; and preventing over current according to detecting result.